The modem broke down a couple days ago and I was wondering what was the issue. I opened up the modem thinking that there would be a burnt component inside but as it was , that wasn't actually the right step. It turned out that it was the adapter that was at fault.
So I had an old one that was like some kind of transformer with various output voltages 3,6, 7.5, 9, 12 being some of them. Adjustments for these adapters are not accurate, for instance the 9V could read 13V. So a multimeter is needed to find out what is the actual output voltage. It is probably not the best way to solve it but it kind of worked for a while. Then I think it got overheated or something,. As it was rated at 350mA, I thought it was the fault of the lack of currrent as the modem seemed to require 12V, 500 mA. This was not the actual case as I found out later that the adapter was able to output more that 500mA current. (around 1A to be exact).
So I went out a couple of times to get another one. There was an adapter rated at 12V 500mA but I settled for the cheaper solution which was another adapter with the adjustable voltages. As it turned out that did not really work - the reason seemed like the voltage output was just a little too low. Its 7.5V would read 12.5V. It appears that though the modem was rated at 12V, it actually needed a minimum of around 13V to function properly.
Fortunately I was able to find another old adapter that was able to output around 13.5 V. It seems to be working fine so far.
Friday, April 29, 2016
Wednesday, April 20, 2016
Revision of Circuits and Electronics - State and Memory (Lecture 16)
Video Lectures: -http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/video-lectures/lecture-14/
Lecture Notes:- (Lecure 14 on OCW but lecture 16 on edX) http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/lecture-notes/
The key is that a capacitor can store a a state for an extended period of time.
The equation for RC charging circuit is v_c=v_c(0)+ (V_I -v_c(0))(1-e^(-t/RC)) . We ignored what happened all the way from minus infinity. v_c(0) was able to summarise the entire behaviour of the input from 0 backwards.
State is the summary of past inputs relevant to predicting the future. q and v are state variables.
v_c was a function of v_c(0) and a function of V_I(t).
Zero state is when v_c(0)=0. Zero input is when V_I(t)=0.
Zero state response (ZSR) occurs at v_c=V_I (1-e^(-t/RC)). The capacitor charges up.
Zero input response(ZIR) occurs at v_c=v_c(0)(e^(-t/RC)). The capacitor discharges.
The sum of the ZSR and ZIR gives the total response of the RC circuit
v_c=V_I+ (v_c(0)-V_I)(e^(-t/RC)). This is a form of superposition.
Why memory? The calculator remembers the partial result. It is needed to remember such results so that things can be done in sequence. Secondly, there is a need to remember transient inputs - signals that come and go away. Finally it is needed to store data.
With this in mind, starting with a simple example, a one bit memory element can be built. It will have d_OUT, d_IN and a STORE signal which tells the memory cell to replace existing value with new value from d_IN.
A camera has a shutter button which helps to store the image. Think of this as a little pulse which opens to allow the image to be appear on the storage medium of the film and when it closes whatever that was recorded will stay in the camera.
Using this analogy, a simple memory cell can be built. Let's say the waveforms for d_OUT, d_IN and STORE start at a low value. When d_IN goes high for a period of time , to store that value, a small STORE pulse can do the job. The STORE pulse is like a shutter release button. d_OUT will reflect what is at the input. The last value that the memory cells saw before the pulse went down to 0 is eventually stored in the memory cell. The output does not go to 1 instantaneously, rather that it meanders up and rises slowly.
In the first attempt to build a memory cell, a capacitor is needed to store a value that is going to be read out, d_OUT. d_IN and a switch is connected to the capacitor. The control input of the s witch is connected to the STORE signal. When the STORE signal has a high value, the switch is closed. If this is a perfectly ideal switch, and this is a true short circuit, and if d_IN comes from an ideal voltage source, then of course I'm going to see my capacitor charging instantaneously. However in pratice that is not the case - the switch has a resistor R_ON. So the capacitor has to charge through R_ON.
Let's say d_IN goes to a 1 and here is my store pulse that stays on for some period of time.
Let's say my dOUT is 0 to begin. As soon as the store pulse goes high, the switch goes into its On state. nd as soon as the switch goes into its On state, now the capacitor C begin surcharge through the resistor R_ON with the time constant, T given by R_ON*C.
As the capacitor begins to charge, the voltage at dOUT starts to rise. So this is the voltage of v_c, which turns out to be the same as d_OUT. So that starts to rise, and when the store pulse goes
Lecture Notes:- (Lecure 14 on OCW but lecture 16 on edX) http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/lecture-notes/
The key is that a capacitor can store a a state for an extended period of time.
The equation for RC charging circuit is v_c=v_c(0)+ (V_I -v_c(0))(1-e^(-t/RC)) . We ignored what happened all the way from minus infinity. v_c(0) was able to summarise the entire behaviour of the input from 0 backwards.
State is the summary of past inputs relevant to predicting the future. q and v are state variables.
v_c was a function of v_c(0) and a function of V_I(t).
Zero state is when v_c(0)=0. Zero input is when V_I(t)=0.
Zero state response (ZSR) occurs at v_c=V_I (1-e^(-t/RC)). The capacitor charges up.
Zero input response(ZIR) occurs at v_c=v_c(0)(e^(-t/RC)). The capacitor discharges.
The sum of the ZSR and ZIR gives the total response of the RC circuit
v_c=V_I+ (v_c(0)-V_I)(e^(-t/RC)). This is a form of superposition.
Why memory? The calculator remembers the partial result. It is needed to remember such results so that things can be done in sequence. Secondly, there is a need to remember transient inputs - signals that come and go away. Finally it is needed to store data.
With this in mind, starting with a simple example, a one bit memory element can be built. It will have d_OUT, d_IN and a STORE signal which tells the memory cell to replace existing value with new value from d_IN.
A camera has a shutter button which helps to store the image. Think of this as a little pulse which opens to allow the image to be appear on the storage medium of the film and when it closes whatever that was recorded will stay in the camera.
Using this analogy, a simple memory cell can be built. Let's say the waveforms for d_OUT, d_IN and STORE start at a low value. When d_IN goes high for a period of time , to store that value, a small STORE pulse can do the job. The STORE pulse is like a shutter release button. d_OUT will reflect what is at the input. The last value that the memory cells saw before the pulse went down to 0 is eventually stored in the memory cell. The output does not go to 1 instantaneously, rather that it meanders up and rises slowly.
In the first attempt to build a memory cell, a capacitor is needed to store a value that is going to be read out, d_OUT. d_IN and a switch is connected to the capacitor. The control input of the s witch is connected to the STORE signal. When the STORE signal has a high value, the switch is closed. If this is a perfectly ideal switch, and this is a true short circuit, and if d_IN comes from an ideal voltage source, then of course I'm going to see my capacitor charging instantaneously. However in pratice that is not the case - the switch has a resistor R_ON. So the capacitor has to charge through R_ON.
Let's say d_IN goes to a 1 and here is my store pulse that stays on for some period of time.
Let's say my dOUT is 0 to begin. As soon as the store pulse goes high, the switch goes into its On state. nd as soon as the switch goes into its On state, now the capacitor C begin surcharge through the resistor R_ON with the time constant, T given by R_ON*C.
As the capacitor begins to charge, the voltage at dOUT starts to rise. So this is the voltage of v_c, which turns out to be the same as d_OUT. So that starts to rise, and when the store pulse goes
away, that value will be held out there.
We need to find out the width of the store pulse. v_c=V_S (1-e^(-t/RC)) as this is a zero state response. The store pulse has to be wide enough for the v_c to charge to its valid high value V_OH.
Therefore V_OH=V_S (1-e^(-t_min/RC)) . The pulse width needs to be much larger than t_min to give enough leeway for the capacitor to reach its final value.
Now with the store =0, we need to find out how long is the charge going to sit on the capacitor. Suppose that the output is connected to some other circuit that has a load resistance R_L. In this case the capacitor will be discharging from a value V_S to a valid value V_OH. So we will need to find t_valid.
v_OH=V_S (e^(-t_valid/(R_L*C))) as this is a zero input response. Therefore t_valid=-R_L*C* ln(V_OH/V_S). This method does not really work as the capacitor discharges very quickly.
The second attempt is to add a pair of inverters (a buffer) to the output. The buffer has a large input resistance R_IN. The time constant is calculated to be about 1 millisecond which would give a better result for t_valid but still not good enough.
For the third attempt, the value is fed back to refresh the node. There is a switch that is connected to STORE bar in this loop. When STORE is a 0, the same value at the output is recycled to the capacitor and the capacitor is meant to be refreshed. This does not work because the external value can influence the storage node.
For the fourth attempt, the feedback loop is now placed after the first inverter and is connected to another inverter and a switch. The switch is connected to STORE bar. This works as there is no path from the output to the input as it is completely decoupled using the inverter. This is a static random access memory (SRAM) where the value of the memory cell stays valid for a long period of time.
An abstract 4 bit memory cell has an input, an output, a STORE signal and an address line. The address tells me which of the four bits of memory I am going to read or write. So the address is given by two bits 00 , 01 , 10 and 11. 00 will read to memory cell 1, 01 to memory cell 2 and so forth. If my address says two and if store is false, then my output should read the second memory cell. Similarly, if the address is two and store is on, then I should be writing into my memory cell two.
So to build the memory system, four memory cells are needed. The one bit output is connected to the four memory cells with switches A, B, C and D. The values of A, B, C and D are produced with a decoder. The address will be the input to the decoders while the outputs are connected to the A, B , C and D switches.
The INPUT is going to be connected to all d_IN. Then there will be AND gates which will be connected to the STORE signal and one of the the outputs of the decoder.
So let's take a look at how this works. So that say the address is 1, 0. If the address is 1, 0, then C is true. And when the store pulse comes on, both inputs are a one. And I get a store pulse on this memory cell. And then whatever's on the input line gets written on to that memory cell. And then following that, if I'll reread the memory cell, I make the store pulse go away. And if C is true, then the switch turns on. And the value can be read out on OUT.
From the truth table, at any given point in time, only one of A, B, C, or D is a 1. Memory cells
containing billions of memory elements are built using similar logic.
v_OH=V_S (e^(-t_valid/(R_L*C))) as this is a zero input response. Therefore t_valid=-R_L*C* ln(V_OH/V_S). This method does not really work as the capacitor discharges very quickly.
The second attempt is to add a pair of inverters (a buffer) to the output. The buffer has a large input resistance R_IN. The time constant is calculated to be about 1 millisecond which would give a better result for t_valid but still not good enough.
For the third attempt, the value is fed back to refresh the node. There is a switch that is connected to STORE bar in this loop. When STORE is a 0, the same value at the output is recycled to the capacitor and the capacitor is meant to be refreshed. This does not work because the external value can influence the storage node.
For the fourth attempt, the feedback loop is now placed after the first inverter and is connected to another inverter and a switch. The switch is connected to STORE bar. This works as there is no path from the output to the input as it is completely decoupled using the inverter. This is a static random access memory (SRAM) where the value of the memory cell stays valid for a long period of time.
An abstract 4 bit memory cell has an input, an output, a STORE signal and an address line. The address tells me which of the four bits of memory I am going to read or write. So the address is given by two bits 00 , 01 , 10 and 11. 00 will read to memory cell 1, 01 to memory cell 2 and so forth. If my address says two and if store is false, then my output should read the second memory cell. Similarly, if the address is two and store is on, then I should be writing into my memory cell two.
So to build the memory system, four memory cells are needed. The one bit output is connected to the four memory cells with switches A, B, C and D. The values of A, B, C and D are produced with a decoder. The address will be the input to the decoders while the outputs are connected to the A, B , C and D switches.
The INPUT is going to be connected to all d_IN. Then there will be AND gates which will be connected to the STORE signal and one of the the outputs of the decoder.
So let's take a look at how this works. So that say the address is 1, 0. If the address is 1, 0, then C is true. And when the store pulse comes on, both inputs are a one. And I get a store pulse on this memory cell. And then whatever's on the input line gets written on to that memory cell. And then following that, if I'll reread the memory cell, I make the store pulse go away. And if C is true, then the switch turns on. And the value can be read out on OUT.
From the truth table, at any given point in time, only one of A, B, C, or D is a 1. Memory cells
containing billions of memory elements are built using similar logic.
Saturday, April 16, 2016
Deleted draft!
I accidentally deleted my notes for lecture 16 and so it will take some time for the next post to come out.
I will try and run though it quickly and post by next week.
Saturday, April 2, 2016
Revision of Circuits and Electronics - Ramps, Steps and Impulses (Lecture 15)
Video and lecture notes:- edX MITx: 6.002.2x Circuits and Electronics 2: week 4
We will find out later why a slower input results in less glitches.
It turns out that circuits can be used to model many real-life situations - the syringe and the drug can be modeled as a current source that is going to be dumping some charge. So it is an injection. And then the body can be modeled as a capacitor. So this is the body storage. So the body can be modeled as a capacitor where, when the syringe injects some drug, and in the electrical analogy when
the current source provides some current, that will then go and charge the capacitor and put the
charge in the capacitor. In the body situation, the injection will deposit some drug in the body.| Once a drug is deposited in the body, the way in which the drug is dissipated through the body is modeled with a little resistor where the drug is then finally dissipated. So it can all be modeled as a first-order RC circuit.
It is possible to model the input as a short pulse as input time duration does not matter. What matters is how much charge is deposited by the pulse. This type of pulse is called as an impulse.
There are several kinds of input-step, impulse, pulse and ramp.
A step input is one in which the signal has been 0 for some time and at a time 0, the signal goes to some d.c.value, say a 1. Then if the signal is V_I(t), it can be written as V_I(t) = u ( t).
If the signal has been 0 for some time and at a time 0, the signal goes to some d.c.value, say V_I, then V_I(t) = V_I*u ( t).
We will find out later why a slower input results in less glitches.
It turns out that circuits can be used to model many real-life situations - the syringe and the drug can be modeled as a current source that is going to be dumping some charge. So it is an injection. And then the body can be modeled as a capacitor. So this is the body storage. So the body can be modeled as a capacitor where, when the syringe injects some drug, and in the electrical analogy when
the current source provides some current, that will then go and charge the capacitor and put the
charge in the capacitor. In the body situation, the injection will deposit some drug in the body.| Once a drug is deposited in the body, the way in which the drug is dissipated through the body is modeled with a little resistor where the drug is then finally dissipated. So it can all be modeled as a first-order RC circuit.
It is possible to model the input as a short pulse as input time duration does not matter. What matters is how much charge is deposited by the pulse. This type of pulse is called as an impulse.
There are several kinds of input-step, impulse, pulse and ramp.
A step input is one in which the signal has been 0 for some time and at a time 0, the signal goes to some d.c.value, say a 1. Then if the signal is V_I(t), it can be written as V_I(t) = u ( t).
If the signal has been 0 for some time and at a time 0, the signal goes to some d.c.value, say V_I, then V_I(t) = V_I*u ( t).
If the signal has been V_I for some time and at a time 0, the signal goes to some 0, then
V_I(t) = V_I - V_I*u ( t). This is a falling step.
If the signal has been 0 for some time and at a time T_0, the signal goes to some some dc value, say a 1, then V_I(t) = u (t - T_0). This is a translated step.
When analyzing RC response to a rising step, we need to find out the voltage of the capacitor just before the step rises, v_c(0-).
It's been 0 for a long period of time- if there had been any voltage across the capacitor, it would
have discharged through the resistor, so therefore the initial condition on the capacitor is v_c(0-), is 0 volts.
After a long period of time, the input takes a step, the voltage will be V_I . The capacitor will charge up fully to V_I. The output is going to be of the form v_c= V_I(1-e^(-t/RC)) .
The circuit can be transformed into a Norton form. After a long period of time, the input takes a step, the current will be I. The capacitor will charge up fully to IR. Then the current, I, will begin flowing to the resistor and cause a voltage IR across the resistor. The output across the capacitor is going to be of the form v_c= I R(1-e^(-t/RC)) .
For the RC response to a falling step, the Norton style of the circuit is used. The reason a current source is used is that, for impulses, it makes it a little easier to think in terms of depositing charge on the capacitor.
When analyzing RC response to a falling step, we will also need to find out the voltage of the capacitor just before the step falls, v_c(0-).
After a long period of time, the capacitor looks like an open, so v_c(0-)=IR.
Then at time t equal to 0, the input goes down to 0. The capacitor that has an initial voltage IR across it, will now discharge through the resistor. The output across the capacitor is going to be of the form v_c= I R(e^(-t/RC)) .
For the RC response to a pulse input which starts at t=0 and has a long pulse width (more than time constant RC), the output across the capacitor is going to be of the form v_c= I R(1-e^(-t/RC)) in the beginning and then later v_c= I R(e^(-(t-T)/RC)) where T is the pulse width.
For the RC response to a pulse input which starts at t=0 and has a shorter pulse width (less than time constant RC), the output across the capacitor is going to be of the form v_c= I R(1-e^(-t/RC)) in the beginning and then later v_c= I R(1-e^(-T/RC)) *(e^(-(t-T)/RC)) where T is the pulse width.
(the point where the waveform starts to discharge is I R(1-e^(-T/RC)) )
Looking at the current pulse, we can see that the area of the pulse is Q. It is possible to make a pulse deliver the same charge when it is made more narrow, to the point that it becomes an impulse.
For the RC response to an impulse input, the waveform is v_c= Q/C(e^(-t/RC)). At t=0, v_c is at Q/C and analysis is done with Taylor series.
v_c(t) is largely independent of T. The capacitor behaves like a short circuit for changes that are much faster than the time constant. All charge goes to the capacitor V=Q/C. The impulse sets up initial conditions for the capacitor.
Current impulse delivers charge while voltage impulse delivers flux linkage. For the RL response to an impulse input, the waveform is i_L= λ/L(e^(-Rt/L)). In this case, the inductor behaves like an instantaneous open.
Superposition does not apply when initial conditions exist. It does apply when initial conditions are zero. One way of solving circuits with with multiple sources and
multiple initial conditions is the following:-
(1) Treat initial conditions like sources.
(2) Find the response to each source or each initial condition acting alone and then sum the partial response.
The notation for an impulse is δt. The notation for unit pulse is u(t) and the notation for ramp is tu(t). The other way of representing them are u_0(t) for impulse, u_-1(t) for unit pulse and u_-2(t) for ramp.
Integrating an impulse produces a step. Integrating a step produces a ramp.
For a linear system, differentiating the input will get the same output differentiated. If the input is integrated, then the corresponding output is integrated as well. This provides another way of finding the output, especially for ramps.
If there is an input that looks like a step and a ramp on top of the step, first find the response to a step. and integrate it to get that of a ramp. Then I add the two up. So using superposition, it is possible get the outputs for all kinds of inputs.
Going back to the slower may be better topic, one can see how parasitic capacitance between two pins of a chip can affect a circuit. Consider R_1 to be the resistance of the wire for pin l and R_0 to be the load resistance and that they are connected to a near ideal voltage source. Also consider pin 2 having a system consisting of an ideal voltage source with a much higher frequency waveform and a resistance R_2. The wires of pin 1 and pin 2 are so close together that they form a parasitic capacitance which causes crosstalk.
Crosstalk is when a signal on one wire influences the signal on another wire when it's not supposed to do so. By superposition, R_1 is in parallel with R_0 and is in series with the parasitic capacitance and the source with a much higher frequency waveform. Taking R_1 in parallel with R_0 to be equal to R. The voltage across the resistor is V_R=V_I*e^(-t/RC) which is an exponential decaying form. The positive spike corresponds to the rising edges of the source waveform while the negative spikes correspond to the falling part of it. These spikes are superimposed on top of the waveform due to the other voltage source.
Slowing down the edges of waveforms to that of triangular waveforms will produce a waveform with less glitches. ( no change in frequency)
Taking 1/A as a constant value to control the slope, integrating the step input will result in a ramp of the form (V_I*t)/A. Then by integrating the output of the step, the output of the ramp will be V_R= ((V_I*R*C_p)/A)*(1-e^(-t/RC_p)). If RC_p is much less than A then the output of the ramp will be a very small blip.
When analyzing RC response to a rising step, we need to find out the voltage of the capacitor just before the step rises, v_c(0-).
It's been 0 for a long period of time- if there had been any voltage across the capacitor, it would
have discharged through the resistor, so therefore the initial condition on the capacitor is v_c(0-), is 0 volts.
After a long period of time, the input takes a step, the voltage will be V_I . The capacitor will charge up fully to V_I. The output is going to be of the form v_c= V_I(1-e^(-t/RC)) .
The circuit can be transformed into a Norton form. After a long period of time, the input takes a step, the current will be I. The capacitor will charge up fully to IR. Then the current, I, will begin flowing to the resistor and cause a voltage IR across the resistor. The output across the capacitor is going to be of the form v_c= I R(1-e^(-t/RC)) .
For the RC response to a falling step, the Norton style of the circuit is used. The reason a current source is used is that, for impulses, it makes it a little easier to think in terms of depositing charge on the capacitor.
When analyzing RC response to a falling step, we will also need to find out the voltage of the capacitor just before the step falls, v_c(0-).
After a long period of time, the capacitor looks like an open, so v_c(0-)=IR.
Then at time t equal to 0, the input goes down to 0. The capacitor that has an initial voltage IR across it, will now discharge through the resistor. The output across the capacitor is going to be of the form v_c= I R(e^(-t/RC)) .
For the RC response to a pulse input which starts at t=0 and has a long pulse width (more than time constant RC), the output across the capacitor is going to be of the form v_c= I R(1-e^(-t/RC)) in the beginning and then later v_c= I R(e^(-(t-T)/RC)) where T is the pulse width.
For the RC response to a pulse input which starts at t=0 and has a shorter pulse width (less than time constant RC), the output across the capacitor is going to be of the form v_c= I R(1-e^(-t/RC)) in the beginning and then later v_c= I R(1-e^(-T/RC)) *(e^(-(t-T)/RC)) where T is the pulse width.
(the point where the waveform starts to discharge is I R(1-e^(-T/RC)) )
Looking at the current pulse, we can see that the area of the pulse is Q. It is possible to make a pulse deliver the same charge when it is made more narrow, to the point that it becomes an impulse.
For the RC response to an impulse input, the waveform is v_c= Q/C(e^(-t/RC)). At t=0, v_c is at Q/C and analysis is done with Taylor series.
v_c(t) is largely independent of T. The capacitor behaves like a short circuit for changes that are much faster than the time constant. All charge goes to the capacitor V=Q/C. The impulse sets up initial conditions for the capacitor.
Current impulse delivers charge while voltage impulse delivers flux linkage. For the RL response to an impulse input, the waveform is i_L= λ/L(e^(-Rt/L)). In this case, the inductor behaves like an instantaneous open.
Superposition does not apply when initial conditions exist. It does apply when initial conditions are zero. One way of solving circuits with with multiple sources and
multiple initial conditions is the following:-
(1) Treat initial conditions like sources.
(2) Find the response to each source or each initial condition acting alone and then sum the partial response.
The notation for an impulse is δt. The notation for unit pulse is u(t) and the notation for ramp is tu(t). The other way of representing them are u_0(t) for impulse, u_-1(t) for unit pulse and u_-2(t) for ramp.
Integrating an impulse produces a step. Integrating a step produces a ramp.
For a linear system, differentiating the input will get the same output differentiated. If the input is integrated, then the corresponding output is integrated as well. This provides another way of finding the output, especially for ramps.
If there is an input that looks like a step and a ramp on top of the step, first find the response to a step. and integrate it to get that of a ramp. Then I add the two up. So using superposition, it is possible get the outputs for all kinds of inputs.
Going back to the slower may be better topic, one can see how parasitic capacitance between two pins of a chip can affect a circuit. Consider R_1 to be the resistance of the wire for pin l and R_0 to be the load resistance and that they are connected to a near ideal voltage source. Also consider pin 2 having a system consisting of an ideal voltage source with a much higher frequency waveform and a resistance R_2. The wires of pin 1 and pin 2 are so close together that they form a parasitic capacitance which causes crosstalk.
Crosstalk is when a signal on one wire influences the signal on another wire when it's not supposed to do so. By superposition, R_1 is in parallel with R_0 and is in series with the parasitic capacitance and the source with a much higher frequency waveform. Taking R_1 in parallel with R_0 to be equal to R. The voltage across the resistor is V_R=V_I*e^(-t/RC) which is an exponential decaying form. The positive spike corresponds to the rising edges of the source waveform while the negative spikes correspond to the falling part of it. These spikes are superimposed on top of the waveform due to the other voltage source.
Slowing down the edges of waveforms to that of triangular waveforms will produce a waveform with less glitches. ( no change in frequency)
Taking 1/A as a constant value to control the slope, integrating the step input will result in a ramp of the form (V_I*t)/A. Then by integrating the output of the step, the output of the ramp will be V_R= ((V_I*R*C_p)/A)*(1-e^(-t/RC_p)). If RC_p is much less than A then the output of the ramp will be a very small blip.
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