Circuits and Electronics - Energy and CMOS Design (Lecture 27)

Video and lecture notes:- edX    MITx: 6.002.3x Circuits and Electronics 3:  week 6

How do we get rid of the static power of our inverter?

So first  draw the equivalent circuit for the inverter when the MOSFET is in its on state.
That will be the case when the input is high. And the average power is going to be V_S squared divided by RL plus R on. RL is usually much bigger than R on, so the power will be
approximately VS squared divided by RL.
So this is my problem case.

When the input is low, then the MOSFETis in its off state. The average power in this case is zero.

However, in the former situation, I don't have any switch, and so therefore, I get this current flow from V_S to ground, and that's not a good situation.


So the question, then, is how do I somehow change this situation? So here is the trick.
What if, in place of RL,  I could get a switch in there. And somehow, when vI was high, the switch was open. If I could get my pull up switch to go open for the input being high, then I would have accomplished my goal. In that situation, I get no static power being burned when the input is high.
So this is good.


So in order to figure out what to use, I'm going to first show you a little bit more about the MOSFET that we have been using. The MOSFET that we have been using is called the N-channel MOSFET.
This is also called an NFET. So the NFET is complimentary to something else called the
PFET or the P-channel MOSFET.  Let me first very quickly review the properties of the N-channel MOSFET. And this MOSFET is on when V_GS is greater than or equal to V_T. The same MOSFET is off when V_GS less than V_TN.

Now let's take a look at something else-- a new device, a device that we haven't seen so far.
This device is called a P-channel MOSFET. In this case, the P-channel MOSFET doesn't have a channel where electrons carry current. And the P-channel creates a channel in the MOSFET where
the current is carried by what are called holes. Hole is an absence of an electron. And in some respects, it kind of behaves like a postive charge. The P-channel MOSFET is also called the PFET.
The PFET has complimentary properties to the N-channel MOSFET. And in the case of the P-channel MOSFET, it is on when V_GS is less than equal to a threshold voltage, V_T. The switch is off when V_GS is greater than V_T.

So now that we have this new complimentary gate, the P-channel MOSFET, let us consider
the following circuit. What I'm going to do, in this circuit I'm going to replace
our usual pull-up resistor with a PFET. And I had a N-channel MOSFET connected.

We can study  the behavior of the circuit by drawing out the equivalent circuit under the situation that v_I is high, and the second situation, v_I being low. We will find that this does not have static power.

But then, as we try to build chips with more and more gates in them at higher and higher frequencies, we realize that even those chips, their power kept increasing as well. And so we had to do something about the dynamic power too.



And it turns out that I'm going to do something about my voltage, and I'm going to do something about my capacitance.

Reducing voltage is not going to last all that long. One trade off, though, is as I reduce the voltage, as I go lower and lower in terms of my voltage, I cannot run my circuit as fast. That's a trade off.
In other words, in the same technology, a supply of 0.7 volts will result in a slower chip than a
supply of one volt.

 We can do something about the capacitance. And it turns out that, as I shrink my process--
recall that the reason I can put more and more transistors on a chip is because I use what I call process shrinks, I make my transistors smaller and smaller with each process generation.

And it not only shrinks the transistor, but recall the capacitor relates to the gate area of the transistor, and the transistor is shrinking, so is the capacitance. If we shrink my capacitors substantially, we can reduce my power significantly as well.

There's more tricks that people play. And one of the example tricks is when the circuit is not in
use, we just turn off the clock, and you go into standby mode.

Not only that, but when you are running the circuit, if some piece of the circuit is not in use-- so let's say for example, I am busy doing bit-level logic operations. If I'm doing bit-level logic operations, perhaps my floating point multiplier unit is not in use, and so I can turn off the clock to my floating point multiplier. So that concept where I turn off the clock to certain parts of the circuit is called clock gating. What I do is I pass my clock through a gate to some piece of the circuit. So I can turn off the clock with the clock enable signal.


There are other tricks that people follow today, and one of those is you change V_S depending on need. The problem is that the lowest voltage will result in the circuit not running fast enough.
So what I could do is, by default, have the circuit running at a low voltage and a low clock speed, and its performance is pretty mediocre. But when I really, really need the performance-- let's say, for example, the user is running a presentation and there's a video that has to be shown involving a lot of
computation. During those times, what I can do is up the voltage and up the frequency so the user can get a bit of a performance boost. But the power will be high as well, but it will be high only for a short period of time.

 notice that from 5 volts, chips in the 2007, 2008 time frame and beyond have gone down to about 1 volt, and as we go from 2012 to '13, '14 and '15, the voltage will go down further, to about 0.8,
0.7, and possibly even 0.6, 0.5 volts, in the middle part of the decade, now in 2014 or 2015.
But it is getting very, very difficult to lower the voltage beyond that. So the key point here with these real numbers is that, by reducing the capacitance, as we've gone from a 700 nanometer technology generation to a 45 nanometer technology generation for the Intel Nehalem, the 8 core
part, or the Tilera 64 core part, we've gone down to very low voltages.

Notice that transistors have gone up by almost a factor of 1,000, 2.5 million to over a billion transistors. Frequency has also gone up by a substantial factor, from 66 megahertz by 50 times, almost 100 times, to 3 gigahertz and beyond. But the power has stayed more or less the same, because all the tricks of the trade that I've talked previously have been applied. So the one point I wanted to make and not leave you with the impression that CMOS logic has only dynamic power.
I want to point out that in recent times, as transistors have gotten smaller and smaller, as they're heading to 45 nanometers, 32 nanometers, 22 nanometers and beyond, we do get to see something called leakage. Leakage causes a form of static power. And the leakage happens because, as the transistors get smaller and smaller, some amount of current can blast through the gate of the transistor, even when the transistor is off. Simply think of it as the gate having a very  high resistance, a non-zero high resistance. And when you have more than a billion transistors on a chip, even if the resistance is very, very high, you have a billion transistors sitting, leaking ever so slightly, you have some leakage power.

So if this is my transistor, and the transistor is on, I get a R_on. R_on is very low. Very low resistance. However, when the transistor is off, ideally I'd like infinite resistance. However, in reality, I end up with R off, which is high, but not open circuit. That causes a small leakage current. And when you have billions of transistors, and getting to two, three, four, eight billion transistors in a chip,
and if each of those transistors is sitting around leaking even slightly, you can have a substantial amount of leakage power, which has become the new static power.

The leakage related static power can be anywhere from 5% all the way up to 50% or 60% of the power. What is interesting about the leakage is that this relates to temperature. As the temperature increases, leakage increases.

So the interesting part is, my leakage goes up, my power goes up. And as my power goes up, my chip temperature goes up. As my chip temperature goes up, my leakage goes up. So this ends up being a little bit of a positive loop like system, and can hurt chips quite significantly if they're not designed very carefully to take into account the negative effects of leakage current

The last part is a review of  CMOS logic design where a NAND gate can be implemented by two PFET in parallel and two NFET in series.

Circuits and Electronics - Energy and Power (Lecture 26)

Video Lectures: -  https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/video-lectures/lecture-22/

Lecture Notes: -  https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/lecture-notes/


This sequence will pull together a lot of what you have learned throughout this course.
And look at it from the energy and power standpoint. Energy is extremely important.

So for example, if you have devices like your handheld, or your laptop, and other such stuff, energy relates to how long the battery will last in your cellphone. How long the battery will last in your laptop. The battery life relates to two things. One is, you've seen in cellphone usage when you look
at the specs of your cellphone, it talks about how long the phone the last in standby mode.
That means when you're not actively talking on your phone, if you just leave the phone on but you don't use it.

Another aspect of energy and power is when we build chips, oftentimes we don't care so much about battery life, but simply if the chip is consuming too much power,


Finally, a really important point is that we really need to reduce our energy consumption. In this sequence we will learn about how we can calculate the amount of energy and power consumed by the kind of circuits we've been building. And then look at ways in which we can reduce the power
substantially.

 We will study energy and power dissipation, and use the MOSFET gate as an example.
So here on the right-hand side, you see a MOSFET gate. It's an inverter. So we have the pull-up resistor here.

What I've also done here is I'm showing you a capacitor, C, that I'm connecting between the output and the ground for this inverter. This capacitor might combine a set of capacitors connected to
the output. So for example, this capacitor might include the capacitance of the gate of a MOSFET that it might be driving. This capacitance also includes the capacitance of the wire or the wires connected to the output of the inverter. So think of this capacitor, C, as the total capacitance
connected to the drain of the MOSFET or the output of the inverter.

So what I'm going to focus on here is I'm going to determine both the standby power, or static power, and the active use power. So standby power relates to the power consumed by the inverter when it is not in active use. In our context here, it means the following. It means that if I keep the input at 0 or 1. I'm not going to change the input.  Clearly, if the input is a 0, then the MOSFET is going to be in its off state, and it's not going to burn any power, any standby power. This is also called static power.

So the standby power, or static power, has to do with when I don't change any of the inputs to my devices, and it's just sitting there idle. And the static, or standby, power relates to the power
consumed in that state.

Then there is the active use power. For active use power, let us say I supply some time varying input.
Let's say I supply a sequence of 1's and 0's. Let's say I apply a square wave, which is a sequence of
1's and 0's. And when that happens, when the MOSFET is switching on and off, there is some extra power consumed by the inverter-- and we'll see why that is the case-- when it's switching back and forth. This is called active use power. We will look at both cases.

So the first example that I want to do is a very, very simple example that you saw in the very
beginning of this course. So in this example, I'm going to have a voltage source. Imagine it's a DC source, an even simple example, connected to a simple resistor. So let's try to figure out two things.
One, let's figure out, just as a quick review, what is the power dissipated in the resistor. Second, what I want to do is once we compute the power dissipated in the resistor, I want to find out what is the
energy dissipated in the resistor in some given period of time.

Remember, the power is the rate of consumption of energy. So we can also figure out what the energy dissipated is in some interval of time T. This is very simple.

So I'd like you to switch to a little exercise where you can try out this conceptual problem yourself and try to solve for both the power and the energy dissipated in the resistor time T.


So the power burned by the resistor- consumed in the resistor is simply the voltage across the resistor times the current into the positive terminal of the voltage, as I've labeled across the resistor. So power is simply P equals voltage times the current. So the energy would simply be the power, in this case P,
times T. And since power is voltage times the current, the energy will be VIT.

The voltage is in volts, the resistor is in ohms, and the power will be in watts.

So the next example I'd like to do is look at the static power dissipated in our gate based on the example that we have just seen. So for our gate, let's try to figure out what the static power is on the standby power. The static power is simply the power consumed by the gate when it is not switching.
In other words, when I don't have some kind of a one zero or other pattern that is making the gates switch. So the choice is either zero or a one at the input to figure out the static power. So for our gate, I can write down two situations. When the input is high, here is my situation. I still have Vs over here. My load resistor Rl- this should be l over here. And when the gate is turned on, the MOSFET is on, I have the MOSFET in its on state. I'm using the SR model for the MOSFET.

So let me write that down as the SR model being used. So I have an Ron for my MOSFET.
Here is when I take my output Vo. I have my input Vi with respect to ground. OK? And this is in its high state. It's one. So when it's a one, the MOSFET is on and the situation I've drawn here is the one that applies to the gate. So in this situation, based on the previous little example that we did, the power P simply going to be Vs squared divided by the resistance through which the voltage is
connected to ground. So it is simply Vs squared and I have a pair of resistors, Rl and Ron.
So I get Rl plus Ron here. So that is my power consumed by the gate when the input is in its high state.

The second situation is when the input is low, so Vi is in its low state. Under those conditions, the MOSFET is going to operate like an open switch. It still has the resistor Ron but the MOSFET will be in its open state. And from here, I connected to Rl as usual and this goes to Vs and this is my output, V not. So in this situation, where is the power being consumed by the inverter here?
The static power here is simply zero. And the power is zero because there is no current flowing
from Vs to ground because of the open circuit that is the
open MOSFET.

So, in general, if I have a bunch of inverters and a bunch of gates in my circuit, if the input to the gate is high, then I'm going to get some static power being burned by the inverter or other gate.
On the other hand, if the input is low, the MOSFET is going to be high, MOSFET is going to be in its open state and it is not going to burn any power. So in general if I have 1,000 gates in my circuit --
imagine there are 1,000 inverters-- then if I pick voltages, inputs randomly then to be zero or a one, half the MOSFETs are expected to have one at their input and the other half will have zero at
their input. So, by and large, half the MOSFETs will be burning power and half will not. And so, therefore, I take the amount of power consumed by one MOSFET and multiply that by half the inverters to find the expected power dissipation of the circuit.

In the next example, I'm going to be beginning to introduce dynamic power or active power.

 In the previous video, we looked at the static power for the MOSFET gate, that is, when the inputs were a 0 or a 1. Now what I'm going to do is I'm going to do a slightly different example. In this example, I'm going to lead up towards how to compute the dynamic power of the inverter. That is when the input to the inverter is switching between 1's and 0's.

Now, doing that for the inverter directly is a little more complicated . And so we are  going to start with a much simpler circuit and build up intuition in terms of how to compute the power that gets dissipated because I'm switching a capacitor, charging and discharging a capacitor.

So the circuit that I'm going to use is going to be the following. I take a voltage source, a VS. I'm going to connect that to a switch, S1. And then I'm going to connect that to a resistor, R1.
And that, in turn, will connect to a capacitor with capacitance C and complete the circuit
for the voltage source. Then I take the connection between the resistor R1 and the capacitor and connect it to a second switch, S2, which, in turn, will go to another resistor and then connect that
back, like so, a resistance R2. All right, what we are  going to do next is  we are going to switch
switches S1 and S2 in the following manner. We are going to first switch S1 on and S2 off.
So I'll switch S1 on first and S2 off. So by doing so, I'm going to charge up the capacitor.
Then what I'll do is I'll switch off S1 and turn S2 on so that the capacitor now, because S2 is turned on and S1 is off, this capacitor will discharge through R2.


There will be a repetitive cycle. The time period is T.  And our goal will be to find out a couple of things.  One goal will be to find the energy dissipated in each cycle. And the second thing will be to find the average power.

So there are two periods, T1 and T2.  So let me go ahead and start with T1. And I'm going to consider the first case, S1 closed and S2 open.
.
The initial condition on the capacitor  starts off at 0. And as a function of time, the capacitor's
going to charge up. As the capacitor keeps charging up, it looks like a long-term open circuit.
VS will completely charge up the capacitor. And after a long period of time, its final value is going
to settle down at VS And it's going to have some rising transient that look like this.
So the form of that rising transient will be 1 minus e raised to minus T over the time constant.
What are the time constant for this circuit? Well, it's R1 C.

Similarly, I can plot the current i.

Instantaneous power be supplied by source, by the voltage source, is going to be V_S times i.
The voltage times the current is my instantaneous power.  The energy will simply be the time integral of the instantaneous power over that interval of time. And I will integrate that from 0 to T1 dt.

 i is V_S over R1 e raised to minus t over R1 C. So we end up getting integral 0 to T1 and V_S squared divided by R1 e raised to minus t over R1 C dt. We will eventually get C V_S squared.


So what we're really saying here is C V_S squared is the energy supplied by the source, total energy supplied by the source in T1.

So the total energy supplied by the source, C V_S squared, one part of it is stored on the capacitor, which is 1/2 C V_S squared stored on capacitor. Well, since the capacitor is being charged through a
resistor, the other half of the energy must have dissipated in R1. Let E1 be the energy dissipated in R1.

What is interesting here,  is notice that when time T1 is large enough, that these two energies, the energy supplied by the source, the energy dissipated in the resistor, or for that matter, the energy
stored in the capacitor are independent of  resistance R1.

 E2 is the energy dissipated in the resistor R2 during time interval T2. Both E1 and E2 are independent of R2 and both are equal. E1 was half C V_S squared, and so is E2.


Total energy dissipated cycle, where the cycle is T1 plus T2, the total energy, E, will be the sum of the two energies, E1 plus E2, where E1 is the energy lost in T1 and E2 is the energy is lost in T2.
So it's E1 plus E2. And the total is CV_S squared.

What about the average power? The average power is simply going to be the total energy
burned in the whole cycle, T1 plus T2, energy divided by the total time, T. So T is simply T1 plus T2.
Now, recall that T is the reciprocal of the frequency of switching. So, average power is CVS squared f where f is the frequency.

All right, thus far, we examined two examples. In the first example, we just took a voltage source across a resistor and computed the static power. And we showed that directly related to the static power in an invert when it had a one or a zero applied at the input. We did a second example.
In the second example, we took a capacitor and we used a pair of switches to charge and discharge the capacitor. But notice that when switch one was turned on, switch two was turned off. Switch two was turned on, switch one was turned off. That is not quite the situation in the inverter.

So back to our inverter. Our goal was really to find out P for the inverter. And recall again, this capacitor C is the capacitor of the gate capacitance of the gates being driven by this inverter and also any parasitic capacitance of the wires and things like that. So to compute the power in this particular situation, I would like to pick some input - a zero one sequence-   a square wave.

So we need to  figure out the average power.  So let's start by drawing the equivalent circuit for my
little inverter here which consists of viltage source V_S, R_L,  capacitor C and R_ON.

So this equivalent circuit to compute the average power.  So it actually turns out that the derivation of the power consumed by the circuit, first by computing the energy and then dividing by the cycle time t is a little bit more complicated and grubby than the circuit we did earlier.

So we can show that the average power for the circuit is given by this expression. So here we have two terms, Vs squared divided by 2 R_ON plus R_ON plus CVd squared vf, CVs squared f. R_L squared divided by R_ON. plus R_ON. all squared. R_L might be 100 times larger than R_ON. So I'm going to neglect R_ON in comparison to R_L.

I get a very simple expression for P. The term on the right hand side is my dynamic power or
active power. So static power is simply the power being burned in R_L because of a connection from Vs through RL to ground. And then the second term, the dynamic power is because I'm switching the capacitor and putting charge in the capacitor and discharging it. Dynamic power will increase in proportion to f, the frequency. The static power is independent of the frequency and the half term comes-- the half shows up because the static power is consumed only for half the cycle.
The MOSFET is on only for half the time. Notice interestingly, that both the static and dynamic
powers relate to the square of the voltage. What that is saying is that the voltage that I apply has a
profound impact on the power being burned.

The amount of capacitance matters and the frequency matters for the dynamic power. But Vs has a profound impact on the power. Dynamic power can be lowered by reducing Vs and the frequency but
if we change the clock frequency,  then  computational speed goes down as well.

Chips are typically about 10 millimeters on a side, so one square centimeter. The chips are square, flat little pieces of silicon. And then if I take a one centimeter squared area at roughly the surface of the sun, it can be seen that they have the same output power.