It has been really hot over here so I have been resting quite a bit. I have had to place a wet towel on my chest as I seem to be feeling hot in that area.
It gets very hot after 12 noon and reaches its maximum temperature at around 4 pm - my running program has been reduced to 2 miles now. 5km runs can be quite tortuous sometimes, so maybe 2 mile runs could be the right amount. I did not see much of an improvement in stamina doing the 5km runs.
Update 5/5/2016 Have been doing 5 km the last two days since the heat wave ended. 5 km is healthier I suppose but can be quite tortuous sometimes.
Update 7/5/2016 It seems like I have been affected by the hot weather again so it is back to 2 mile runs I guess.
Friday, March 25, 2016
Sunday, March 13, 2016
Revision of Circuits and Electronics - Digital Circuit Speed (Lecture 14)
Video Lectures:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/video-lectures/lecture-13/
Lecture Notes:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/video-lectures/lecture-13/
An intuitive approach can be taken to plot the responses to various inputs. There are two kinds of waveforms for the capacitor or inductor circuits- exponential decay e^(-t/RC) and another one with an expression (1-e^(-t/RC))
Plotting the graph of v_c versus t , for the case V_I > V_0, we can see that the capacitor will charge up, so the waveform with the expression (1-e^(-t/RC)) is picked. The waveform with the expression (1-e^(-t/RC)) starts off at 0 and ends at 1, which looks something like (1-0)(1-e^(-t/RC)) so the capacitor circuit should have (V_I -V_0)(1-e^(-t/RC)) as part of the expression for v_c. It can also be seen from the graph that at time t=0, v_c=V_0 , and (V_I -V_0)(1-e^(-t/RC))=0 so the final equation should be v_c=V_0 + (V_I -V_0)(1-e^(-t/RC)) with V_0 being the initial value.
For the case where V_I0, we can see that the capacitor will discharge, so the waveform with the expression e^(-t/RC) is picked. The waveform with the expression e^(-t/RC) starts off at 1 and ends at 0, which looks something like (1-0)(e^(-t/RC)) so the capacitor circuit should have (V_0 -V_I)(e^(-t/RC)) as part of the expression for v_c. It can also be seen from the graph that at time t=0, v_c=V_0 , and (V_0-V_I)(e^(-t/RC))=(V_I -V_0) so the final equation should be
v_c=V_I + (V_0 -V_I)(e^(-t/RC)).
Applying the result to two inverters, we will need to draw out the circuit, which are two pairs of resistor and MOSFET. The capacitor is between the gate and the source of the MOSFET. There are two delays at B(the input of the second inverter) - the rising delay, the delay when the signal is rising and the falling delay. For cleanliness, the focus will be on the capacitor at B.
Suppose that the voltage at A ( input to the first inverter) is going from 5V to 0V -from logical 1 to logical 0, then the output of it, which is B will switch from logical 0 to logical l. So we will need to figure out the rising delay at this point.
Due to the capacitor at B, the output at B will be a waveform with the expression (1-e^(-t/RC)). The rising delay or t_r is the time taken to reach the valid value for a high signal V_OH.
We need to figure out what is the equivalent circuit that can compute the rise time. It is generally around the output at B. From there, we have to assume that the output at B starts at 0V. So we need to find out how long it takes to go from 0V to V_OH.
When A goes from 5 volts to 0 volts, the MOSFET for the first inverter turns off and so the capacitor at node B starts to charge up from 0 to V_S. Therefore the equation will be v_B= V_S(1-e^(-t/RC)) . So we need to find the time t it takes for v_B to reach V_OH.
The rising delay t_r= R_L*C_GS*ln((V_S-V_OH)/V_S). This value is quite close to the time constant RC so for a quick answer to the value of the rising delay, the time constant can be used.
If t_r=0.16 ns, the frequency will be 1/t_r=6GHz but there are generally 10 to 20 delays, so for 10 delays, the frequency will be 6/10 GHz = 600 MHz.
Next, we need to figure out the falling delay. Falling delay is simply the time for which v_B to fall from V_S to V_OL. So it starts out with the first inverter off, and so v_B has charged up to VS. Now, the moment this inverter switches to its on state, when the input at A goes from 0 to 1 ihen this MOSFET, which comprises gate x, will turn on. As soon as it turns on, then not only do I have a VS
connection through R_L to node B, but also the R_ON resistance. v_B(0)= V_S=5V
Thevenin's theorem can be used. V_TH=V_S (R_ON/(R_ON+R_L)) and
R_TH=(R_L*R_ON)/(R_L+R_ON). The capacitor will discharge from a voltage of V_S to V_TH.
The exponential decay is governed by the time constant RC.
The time constant RC=R_TH*C_GS. the equation will be
v_B= V_TH+(V_S -V_TH)( (e^(-t/(R_TH*C_GS))) . So taking V_B=V_OL , the falling delay
t_f= R_TH*C_GS*ln((V_OL-V_TH)/(V_S-V_TH)).
Once again, the value of the time constant is close to that of t_f. The effect of R_ON has made the time constant smaller resulting in a smaller falling delay (waveform falls faster).
There may be times when slower may be better. A real life example was when a group of students in a university built a chip which had input and output pins. What they were hoping to see from the output was a nice little step from a low voltage to a high voltage. What they saw was a slow rise. So they thought they could make a faster wave by reducing the resistance but what they got was a waveform with many glitches.
The solution was to slow down the edges of the waveform. There was a parasitic capacitance between the pins which had caused the glitches.
Lecture Notes:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/video-lectures/lecture-13/
An intuitive approach can be taken to plot the responses to various inputs. There are two kinds of waveforms for the capacitor or inductor circuits- exponential decay e^(-t/RC) and another one with an expression (1-e^(-t/RC))
Plotting the graph of v_c versus t , for the case V_I > V_0, we can see that the capacitor will charge up, so the waveform with the expression (1-e^(-t/RC)) is picked. The waveform with the expression (1-e^(-t/RC)) starts off at 0 and ends at 1, which looks something like (1-0)(1-e^(-t/RC)) so the capacitor circuit should have (V_I -V_0)(1-e^(-t/RC)) as part of the expression for v_c. It can also be seen from the graph that at time t=0, v_c=V_0 , and (V_I -V_0)(1-e^(-t/RC))=0 so the final equation should be v_c=V_0 + (V_I -V_0)(1-e^(-t/RC)) with V_0 being the initial value.
For the case where V_I
v_c=V_I + (V_0 -V_I)(e^(-t/RC)).
Applying the result to two inverters, we will need to draw out the circuit, which are two pairs of resistor and MOSFET. The capacitor is between the gate and the source of the MOSFET. There are two delays at B(the input of the second inverter) - the rising delay, the delay when the signal is rising and the falling delay. For cleanliness, the focus will be on the capacitor at B.
Suppose that the voltage at A ( input to the first inverter) is going from 5V to 0V -from logical 1 to logical 0, then the output of it, which is B will switch from logical 0 to logical l. So we will need to figure out the rising delay at this point.
Due to the capacitor at B, the output at B will be a waveform with the expression (1-e^(-t/RC)). The rising delay or t_r is the time taken to reach the valid value for a high signal V_OH.
We need to figure out what is the equivalent circuit that can compute the rise time. It is generally around the output at B. From there, we have to assume that the output at B starts at 0V. So we need to find out how long it takes to go from 0V to V_OH.
When A goes from 5 volts to 0 volts, the MOSFET for the first inverter turns off and so the capacitor at node B starts to charge up from 0 to V_S. Therefore the equation will be v_B= V_S(1-e^(-t/RC)) . So we need to find the time t it takes for v_B to reach V_OH.
The rising delay t_r= R_L*C_GS*ln((V_S-V_OH)/V_S). This value is quite close to the time constant RC so for a quick answer to the value of the rising delay, the time constant can be used.
If t_r=0.16 ns, the frequency will be 1/t_r=6GHz but there are generally 10 to 20 delays, so for 10 delays, the frequency will be 6/10 GHz = 600 MHz.
Next, we need to figure out the falling delay. Falling delay is simply the time for which v_B to fall from V_S to V_OL. So it starts out with the first inverter off, and so v_B has charged up to VS. Now, the moment this inverter switches to its on state, when the input at A goes from 0 to 1 ihen this MOSFET, which comprises gate x, will turn on. As soon as it turns on, then not only do I have a VS
connection through R_L to node B, but also the R_ON resistance. v_B(0)= V_S=5V
Thevenin's theorem can be used. V_TH=V_S (R_ON/(R_ON+R_L)) and
R_TH=(R_L*R_ON)/(R_L+R_ON). The capacitor will discharge from a voltage of V_S to V_TH.
The exponential decay is governed by the time constant RC.
The time constant RC=R_TH*C_GS. the equation will be
v_B= V_TH+(V_S -V_TH)( (e^(-t/(R_TH*C_GS))) . So taking V_B=V_OL , the falling delay
t_f= R_TH*C_GS*ln((V_OL-V_TH)/(V_S-V_TH)).
Once again, the value of the time constant is close to that of t_f. The effect of R_ON has made the time constant smaller resulting in a smaller falling delay (waveform falls faster).
There may be times when slower may be better. A real life example was when a group of students in a university built a chip which had input and output pins. What they were hoping to see from the output was a nice little step from a low voltage to a high voltage. What they saw was a slow rise. So they thought they could make a faster wave by reducing the resistance but what they got was a waveform with many glitches.
The solution was to slow down the edges of the waveform. There was a parasitic capacitance between the pins which had caused the glitches.
Wednesday, March 9, 2016
Revision of Circuits and Electronics - Inductors and First-Order Circuits (Lecture 13)
Video and lecture notes:- edX MITx: 6.002.2x Circuits and Electronics 2: week 3
Capacitors and inductors are both energy storage devices. They are duals of each other. The structure of the inductor is a core with a magnetic permeability μ and a coil of wire wrapped around it.
Let's say a current i is flowing through the wire, there is a voltage between the two terminals of the wire, there are N turns of wire , the area of the core is A and the circumference of the core is l.
Let's say that it has a total magnetic flux linked to it called λ. So when a current is passed through this coil of wire, there is a magnetic flux that links with each of these turns of the wire. And add them all up, and a total flux linked called λ is obtained
So the inductance of this is given by (μ N^2 A)/ l. This is quite similar to the equation of capacitance C=eA/d.
For the inductor, there is a relationship between the magnetic flux λ, inductance and current where λ=Li. (Units for λ is Webers and units for L is Henries). This is quite similar to the equation of q=cv for the capacitor.
From Maxwell's equations, v=dλ/dt = L di/dt. This is similar to C dv/dt for capacitors.
i can be expressed in terms of v. i is the integral of v dt multiplied by 1/L with the limits between t and negative infinity.
Power can also be computed. P=vi= iLdi/dt). From integration, E=(L*i^2)/2. This is similar to
E=(c*v^2)/2 for the capacitor. This is an important equation as it proves that the inductor is an energy storage device. This also makes it a memory device. It stores energy and that energy it stores, remembers what had happened before.
Inductor L is connected to a the voltage source v(t). The current flowing into the inductor is i(t). The initial current flowing in the inductor is i(t_o).
We need to pick some voltage-a pulse which has a height of V for some amount of time T. We need to find i(t) for this input voltage.
To do that, we need to use the integral ofv dt multiplied by 1/L with the limits between t and negative infinity. By splitting the integral into several parts, the graph of i(t) versus t can be drawn. The height during the time T is VT/L. This is similar to what was obtained for the capacitor IT/C.
Inductors like to hold on to the same current. If a large current is pumped into the inductor, the inductor looks like an instantaneous open and it could breakdown.
Analyzing RL circuits, a Norton equivalent type of circuit is used where a current source, a resistor and an inductor are connected in parallel. Applying the node method and rearranging, we will get a first order differential equation L/R (di_L/dt) +i_L=i_I.
For the next step, a solution to this equation, can be obtained by inspection based on the solution obtained for the capacitor circuit. The initial conditions of the inductor is i_L(0)=I_0 and the input source i_I(t)= I_I. So now we will have a differential equation L/R (di_L/dt) +i_L=I_I. The time constant is L/R.
If we base the solution of the inductor with that of the capacitor, the equation obtained will be i_L=I_I+(I_0 - I_I)e^(-t/τ) where time constant τ = L/R
Capacitors and inductors are both energy storage devices. They are duals of each other. The structure of the inductor is a core with a magnetic permeability μ and a coil of wire wrapped around it.
Let's say a current i is flowing through the wire, there is a voltage between the two terminals of the wire, there are N turns of wire , the area of the core is A and the circumference of the core is l.
Let's say that it has a total magnetic flux linked to it called λ. So when a current is passed through this coil of wire, there is a magnetic flux that links with each of these turns of the wire. And add them all up, and a total flux linked called λ is obtained
So the inductance of this is given by (μ N^2 A)/ l. This is quite similar to the equation of capacitance C=eA/d.
For the inductor, there is a relationship between the magnetic flux λ, inductance and current where λ=Li. (Units for λ is Webers and units for L is Henries). This is quite similar to the equation of q=cv for the capacitor.
From Maxwell's equations, v=dλ/dt = L di/dt. This is similar to C dv/dt for capacitors.
i can be expressed in terms of v. i is the integral of v dt multiplied by 1/L with the limits between t and negative infinity.
Power can also be computed. P=vi= iLdi/dt). From integration, E=(L*i^2)/2. This is similar to
E=(c*v^2)/2 for the capacitor. This is an important equation as it proves that the inductor is an energy storage device. This also makes it a memory device. It stores energy and that energy it stores, remembers what had happened before.
Inductor L is connected to a the voltage source v(t). The current flowing into the inductor is i(t). The initial current flowing in the inductor is i(t_o).
We need to pick some voltage-a pulse which has a height of V for some amount of time T. We need to find i(t) for this input voltage.
To do that, we need to use the integral ofv dt multiplied by 1/L with the limits between t and negative infinity. By splitting the integral into several parts, the graph of i(t) versus t can be drawn. The height during the time T is VT/L. This is similar to what was obtained for the capacitor IT/C.
Inductors like to hold on to the same current. If a large current is pumped into the inductor, the inductor looks like an instantaneous open and it could breakdown.
Analyzing RL circuits, a Norton equivalent type of circuit is used where a current source, a resistor and an inductor are connected in parallel. Applying the node method and rearranging, we will get a first order differential equation L/R (di_L/dt) +i_L=i_I.
For the next step, a solution to this equation, can be obtained by inspection based on the solution obtained for the capacitor circuit. The initial conditions of the inductor is i_L(0)=I_0 and the input source i_I(t)= I_I. So now we will have a differential equation L/R (di_L/dt) +i_L=I_I. The time constant is L/R.
If we base the solution of the inductor with that of the capacitor, the equation obtained will be i_L=I_I+(I_0 - I_I)e^(-t/τ) where time constant τ = L/R
Sunday, March 6, 2016
Revision of Circuits and Electronics - Capacitors and First-Order Systems (Lecture 12)
Video:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/video-lectures/lecture-12/
Lecture Notes:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/lecture-notes/
From a pair of inverters, the output was not as expected. There was some delay in the final output.
Taking a look at the n-channel MOSFET - first, it is made up of silicon which is doped with a p-type material to become a semiconductor. Then put a thin layer of oxide (silicon dioxide) which is an insulator. .
Then another layer is put on the oxide. This layer can be many things. It could be a metal or something called polysilicon - a conductive form of silicon. So that layer is the gate. One can see that it is starting to resemble a capacitor-which has an insulator between two metal plates.
Next, two parts of the the p type are doped with n- type material. It is doped heavily with n type so it becomes a better conductor than the bulk which was reasonably doped.
A positive voltage is applied to the metal in relation to the bulk silicate. A set of positive charges appear at the boundary of the metal.
The positive voltage also attracts negative charges, electrons from the n type region which will migrate into the region close to the oxide, to form a channel. It can be seen that this resembles a capacitor.
The n-type regions are the drain and the source. The capacitor is commonly drawn between the gate and the source and it is called C_gs.
How does the MOSFET really work? If a positive voltage is applied to the drain with respect to the source, the electrons from the source are attracted to the drain. Current moves in the opposite direction to the electrons, so a positive current is flowing from the drain to source. The source produces electrons while the drain takes electrons.
The threshold voltage is where it takes a fair amount of voltage to form a conducting channel.
It is possible to build a capacitor. First, oxide is deposited on the silicon chip substrate. Then a plate is stuck on top of it. It could be a metal plate or polysilicon.
Of course, it is possible to build discrete capacitors by taking a pair of plates and having some insulator between them.
Capacitance is given by (e*A)/d where e is the permittivity of the dielectric, A is the area of the plates and d is the thickness of the dielectric.
When voltage v is applied to the terminals of the capacitor, there is a charge q on the capacitor.
q=Cv where C is the capacitance in farads. It can be considered to be a linear element and obeys the discrete matter discipline (DMD).
According to DMD, there is no net charge in my element but it seems that the capacitor does accumulate charge, so what is going on? If you put a box around the capacitor, it can be seen that the positive charge on one plate is exactly balanced by the negative charge on the other plate so there is no net charge.
Current is the rate of change of charge - i = dq/dt . If we substitute q by Cv, we get i=d(Cv)/dt. Assume that the capacitance is not a function of voltage or time - it has a fixed value and is constant.
So i=C(dv/dt).
v can be expressed in terms of i. v is the integral of i dt multiplied by 1/C with the limits between t and negative infinity.
Power can also be computed. P=vi= vC(dv/dt). From integration, E=(c*v^2)/2. This is an important equation as it proves that the capacitor is an energy storage device. This also makes it a memory device. It stores energy and that energy it stores, remembers what had happened before. The capacitor stores some state.
Capacitors are becoming important in energy storage but it can be harmful.
Capacitor c is connected to a the current source i(t). The voltage across the capacitor is v(t). The initial voltage of the capacitor is v(t_o).
We need to pick some current-a pulse which has a height of I for some amount of time T. We need to find v(t) for this input current.
To do that, we need to use the integral of i dt multiplied by 1/C with the limits between t and negative infinity. By splitting the integral into several parts, the graph of v(t) versus t can be drawn. The height during the time of charging is IT/C.
Circuits with one energy storage element are called first order circuits.
Analyzing RC circuits, it can be seen that the Thevenin's equivalent type of circuit could be used. Applying the node method and rearranging, we will get a first order differential equation RC (dv_c/dt) +v_c=v_I
The initial conditions of the capacitor is v_c(0)=V_0 and the input source v_I(t)= V_I. So now we will have a differential equation RC (dv_c/dt) +v_c=V_I
The method of homogeneous and particular solutions is used to solve the differential equation. The steps are :-
(1) Find the particular solution
(2) Find the homogeneous solution
(3) The total solution is the sum of the particular and homogeneous solution. Use the initial
conditions to solve for the remaining constants
So v_c(t)= particular + homogeneous solution.
The solution involves guesswork.
To find the particular solution, use trial and error on RC (dv_cp/dt) +v_cp=V_I where v_cp is a particular solution. Taking v_cp=V_I, then it seems to work.
The homogeneous solution is one where the drive is set to zero. Trial and error will also be used on RC (dv_ch/dt) +v_ch=0. Assume v_ch= Ae^(st) . Discarding the trivial A=0 solution, we will eventually get a characteristic equation of RCs+1=0. Therefore, s=-1/(RC) or v_ch=Ae^(-t/RC).
RC is a time constant.
From the initial conditions, it will be possible to find the value of A. A= V_0 - V_I
With that we can get the total final solution v_c=V_I+(V_0 - V_I)e^(-t/RC).
We can also get i_c which is equal to i=d(Cv_c)/dt. i_c= -(1/R)*(V_0 - V_I)e^(-t/RC).
To graph the solution, set t=0. It can be seen that v_c=V_0 when t=0. Then, when t is set to infinity, v_c= V_I. Assuming that V_I > V_0, then V_I can be marked on the graph. Between V_0 and V_I, there will be a rising curve.
One interesting aspect of this graph is that if we take the slope at the starting point, and look at where it intersects the final voltage value of the capacitor, that value is RC on the t-axis. Mathematically, this can be proven by differentiating v_c with respect to t at time t = 0.
Another point to note is that the equation v_c can be rewritten in a form of v_c(t) so that
v_c(t)=v_c(∞)+(v_c(0) - v_c(∞))e^(-t/RC). Any of the two forms can be used.
The last point to note is that if V_I < V_0, the curve would go in the opposite direction. If V_I=0, there would be an exponential discharge.
Finally, some examples that relate to the voltage outputs of the pair of inverters. Take the initial voltage v_c(0)=V_0=0V and v_I(t)=V_I=5V. This means that there is no voltage at the capacitor in the beginning and let's say at time t=0 the voltage switches suddenly from 0V to 5V. The curve starts out at 0 and after infinity time it reaches a voltage of 5V. The current across R decreases over time.
The equation for this curve is v_c= 5 - 5e^(-t/RC)
In the next scenario, v_c(0)=V_0=5V and v_I(t)=V_I=0V. If the input voltage V_I has been 5V for a long period of time, the voltage across the capacitor will be 5V. If at time t=0, V_I becomes 0 suddenly, then the capacitor will discharge. The curve starts out at 5V and after infinity time it reaches a voltage of 0 V. There will be an exponential decay. If we take the slope at time t=0 and see where it intersects the final voltage value, the value is time constant RC on the t-axis. The equation for the curve is v_c= 5e^(-t/RC)
If we combine the two curves, we will be able to see why the output of the pair of inverters behave the way they do.
Lecture Notes:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/lecture-notes/
From a pair of inverters, the output was not as expected. There was some delay in the final output.
Taking a look at the n-channel MOSFET - first, it is made up of silicon which is doped with a p-type material to become a semiconductor. Then put a thin layer of oxide (silicon dioxide) which is an insulator. .
Then another layer is put on the oxide. This layer can be many things. It could be a metal or something called polysilicon - a conductive form of silicon. So that layer is the gate. One can see that it is starting to resemble a capacitor-which has an insulator between two metal plates.
Next, two parts of the the p type are doped with n- type material. It is doped heavily with n type so it becomes a better conductor than the bulk which was reasonably doped.
A positive voltage is applied to the metal in relation to the bulk silicate. A set of positive charges appear at the boundary of the metal.
The positive voltage also attracts negative charges, electrons from the n type region which will migrate into the region close to the oxide, to form a channel. It can be seen that this resembles a capacitor.
The n-type regions are the drain and the source. The capacitor is commonly drawn between the gate and the source and it is called C_gs.
How does the MOSFET really work? If a positive voltage is applied to the drain with respect to the source, the electrons from the source are attracted to the drain. Current moves in the opposite direction to the electrons, so a positive current is flowing from the drain to source. The source produces electrons while the drain takes electrons.
The threshold voltage is where it takes a fair amount of voltage to form a conducting channel.
It is possible to build a capacitor. First, oxide is deposited on the silicon chip substrate. Then a plate is stuck on top of it. It could be a metal plate or polysilicon.
Of course, it is possible to build discrete capacitors by taking a pair of plates and having some insulator between them.
Capacitance is given by (e*A)/d where e is the permittivity of the dielectric, A is the area of the plates and d is the thickness of the dielectric.
When voltage v is applied to the terminals of the capacitor, there is a charge q on the capacitor.
q=Cv where C is the capacitance in farads. It can be considered to be a linear element and obeys the discrete matter discipline (DMD).
According to DMD, there is no net charge in my element but it seems that the capacitor does accumulate charge, so what is going on? If you put a box around the capacitor, it can be seen that the positive charge on one plate is exactly balanced by the negative charge on the other plate so there is no net charge.
Current is the rate of change of charge - i = dq/dt . If we substitute q by Cv, we get i=d(Cv)/dt. Assume that the capacitance is not a function of voltage or time - it has a fixed value and is constant.
So i=C(dv/dt).
v can be expressed in terms of i. v is the integral of i dt multiplied by 1/C with the limits between t and negative infinity.
Power can also be computed. P=vi= vC(dv/dt). From integration, E=(c*v^2)/2. This is an important equation as it proves that the capacitor is an energy storage device. This also makes it a memory device. It stores energy and that energy it stores, remembers what had happened before. The capacitor stores some state.
Capacitors are becoming important in energy storage but it can be harmful.
Capacitor c is connected to a the current source i(t). The voltage across the capacitor is v(t). The initial voltage of the capacitor is v(t_o).
We need to pick some current-a pulse which has a height of I for some amount of time T. We need to find v(t) for this input current.
To do that, we need to use the integral of i dt multiplied by 1/C with the limits between t and negative infinity. By splitting the integral into several parts, the graph of v(t) versus t can be drawn. The height during the time of charging is IT/C.
Circuits with one energy storage element are called first order circuits.
Analyzing RC circuits, it can be seen that the Thevenin's equivalent type of circuit could be used. Applying the node method and rearranging, we will get a first order differential equation RC (dv_c/dt) +v_c=v_I
The initial conditions of the capacitor is v_c(0)=V_0 and the input source v_I(t)= V_I. So now we will have a differential equation RC (dv_c/dt) +v_c=V_I
The method of homogeneous and particular solutions is used to solve the differential equation. The steps are :-
(1) Find the particular solution
(2) Find the homogeneous solution
(3) The total solution is the sum of the particular and homogeneous solution. Use the initial
conditions to solve for the remaining constants
So v_c(t)= particular + homogeneous solution.
The solution involves guesswork.
To find the particular solution, use trial and error on RC (dv_cp/dt) +v_cp=V_I where v_cp is a particular solution. Taking v_cp=V_I, then it seems to work.
The homogeneous solution is one where the drive is set to zero. Trial and error will also be used on RC (dv_ch/dt) +v_ch=0. Assume v_ch= Ae^(st) . Discarding the trivial A=0 solution, we will eventually get a characteristic equation of RCs+1=0. Therefore, s=-1/(RC) or v_ch=Ae^(-t/RC).
RC is a time constant.
From the initial conditions, it will be possible to find the value of A. A= V_0 - V_I
With that we can get the total final solution v_c=V_I+(V_0 - V_I)e^(-t/RC).
We can also get i_c which is equal to i=d(Cv_c)/dt. i_c= -(1/R)*(V_0 - V_I)e^(-t/RC).
To graph the solution, set t=0. It can be seen that v_c=V_0 when t=0. Then, when t is set to infinity, v_c= V_I. Assuming that V_I > V_0, then V_I can be marked on the graph. Between V_0 and V_I, there will be a rising curve.
One interesting aspect of this graph is that if we take the slope at the starting point, and look at where it intersects the final voltage value of the capacitor, that value is RC on the t-axis. Mathematically, this can be proven by differentiating v_c with respect to t at time t = 0.
Another point to note is that the equation v_c can be rewritten in a form of v_c(t) so that
v_c(t)=v_c(∞)+(v_c(0) - v_c(∞))e^(-t/RC). Any of the two forms can be used.
The last point to note is that if V_I < V_0, the curve would go in the opposite direction. If V_I=0, there would be an exponential discharge.
Finally, some examples that relate to the voltage outputs of the pair of inverters. Take the initial voltage v_c(0)=V_0=0V and v_I(t)=V_I=5V. This means that there is no voltage at the capacitor in the beginning and let's say at time t=0 the voltage switches suddenly from 0V to 5V. The curve starts out at 0 and after infinity time it reaches a voltage of 5V. The current across R decreases over time.
The equation for this curve is v_c= 5 - 5e^(-t/RC)
In the next scenario, v_c(0)=V_0=5V and v_I(t)=V_I=0V. If the input voltage V_I has been 5V for a long period of time, the voltage across the capacitor will be 5V. If at time t=0, V_I becomes 0 suddenly, then the capacitor will discharge. The curve starts out at 5V and after infinity time it reaches a voltage of 0 V. There will be an exponential decay. If we take the slope at time t=0 and see where it intersects the final voltage value, the value is time constant RC on the t-axis. The equation for the curve is v_c= 5e^(-t/RC)
If we combine the two curves, we will be able to see why the output of the pair of inverters behave the way they do.
Tuesday, March 1, 2016
Revision of Circuits and Electronics - Small signal circuits (Lecture 11)
Video:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/video-lectures/lecture-11/
Lecture Notes:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/lecture-notes/
How to choose a bias point aka operating point? If you want a symetric input swing, choose an operating point in the middle of the input operating range but this does not necessarily produce a symetric output swing.
(1) Gain and (2) input swing are the two points for selecting a bias point. From v_o=- (k*R_L(V_I - V_T))*v_i, higher V_I gives higher gain but input swing may not be symetric.
Recall the 3 steps for the small signal analysis:-
(1) Find the operating point using DC bias inputs from large signal circuit
(2) Develop small signal models for each of the elements around the operating point.
(3) Analyze the linearized circuit to get the small signal response.
In lecture 7, it can be seen how small signal models can be derived from non linear components.
The DC voltage source behaves as a short to small signals. The DC current source behaves as an open to small signals.
The large signal model of the MOSFET makes use of the equation i_DS=k/2 ( v_GS - V_T)^2 .
What is the small signal model for the MOSFET? i_ds is found by differentiating I_DS=k/2 ( v_GS - V_T)^2 w.r.t. v_GS taking v_GS=V_GS and then multiply this value by v_gs. Notice that this is similar to what was done in lecture 7 and end of lecture 10 but in this case i_ds and v_gs are used instead.
The equation i_ds=k ( V_GS - V_T)*v_gs is obtained. What is this device?
g_m is equal to k ( V_GS - V_T) and it is a transconductance as the current through the drain source terminals is controlled by the voltage between the gate source terminals.
Node analysis is used for developing the large signal and small signal model equations. For large signal models, the equations used are i_DS=k/2 ( v_I - V_T)^2 and v_O=V_S - (k/2(v_I - V_T)^2)*R_L (i_DS, v_I, v_O being replaced by I_DS, V_I and V_O respectively) while in the small signal model, the equations are i_ds=k ( V_I - V_T)*v_i and v_o=- (k(V_I - V_T)R_L*v_i)
v_i is not always equal to v_gs as seen from the last example.
Lecture Notes:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/lecture-notes/
How to choose a bias point aka operating point? If you want a symetric input swing, choose an operating point in the middle of the input operating range but this does not necessarily produce a symetric output swing.
(1) Gain and (2) input swing are the two points for selecting a bias point. From v_o=- (k*R_L(V_I - V_T))*v_i, higher V_I gives higher gain but input swing may not be symetric.
Recall the 3 steps for the small signal analysis:-
(1) Find the operating point using DC bias inputs from large signal circuit
(2) Develop small signal models for each of the elements around the operating point.
(3) Analyze the linearized circuit to get the small signal response.
In lecture 7, it can be seen how small signal models can be derived from non linear components.
The DC voltage source behaves as a short to small signals. The DC current source behaves as an open to small signals.
The large signal model of the MOSFET makes use of the equation i_DS=k/2 ( v_GS - V_T)^2 .
What is the small signal model for the MOSFET? i_ds is found by differentiating I_DS=k/2 ( v_GS - V_T)^2 w.r.t. v_GS taking v_GS=V_GS and then multiply this value by v_gs. Notice that this is similar to what was done in lecture 7 and end of lecture 10 but in this case i_ds and v_gs are used instead.
The equation i_ds=k ( V_GS - V_T)*v_gs is obtained. What is this device?
g_m is equal to k ( V_GS - V_T) and it is a transconductance as the current through the drain source terminals is controlled by the voltage between the gate source terminals.
Node analysis is used for developing the large signal and small signal model equations. For large signal models, the equations used are i_DS=k/2 ( v_I - V_T)^2 and v_O=V_S - (k/2(v_I - V_T)^2)*R_L (i_DS, v_I, v_O being replaced by I_DS, V_I and V_O respectively) while in the small signal model, the equations are i_ds=k ( V_I - V_T)*v_i and v_o=- (k(V_I - V_T)R_L*v_i)
v_i is not always equal to v_gs as seen from the last example.
Monday, February 29, 2016
Revision of Circuits and Electronics - Amplifiers - small signal model (Lecture 10)
Video:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/video-lectures/lecture-10
Lecture Notes:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/lecture-notes/
To make the MOSFET operate in the saturation region, the signal first needs to be boosted by applying a DC value, a DC voltage source, V_I , then after that apply a signal of interest, V_A which operates within the saturation region.
The output is an inversion of the input and there is a fair bit of distortion as the saturation region is not a straight line. There is amplification for sure but the signal is distorted so the amplifier is non linear.
How do we get a linear amplifier? This can be done with the small signal trick, where we focus on a small piece of the non-linear curve. So after boosting with a DC voltage, the input voltage needs to be shrunk to a small signal that gives a linear response.
Let's look at the small signal method
(1)graphically, (2) mathematically, and (3) from a circuit viewpoint - in the next sequence.
(1) Graphically, recall the small Signal Model Notation where v_I (total variable)= V_I (dc bias) + v_i (small signal) and v_O=V_O + v_o. From this method we will notice that a linear output can be obatined.
(2) Mathematically, first we need to substitute v_I=V_I+ v_i into
v_O=V_S -( k/2(v_I - V_T)^2)*R_L. The Bias Point Equation is V_O=V_S - (k/2(V_I - V_T)^2)*R_L and this is marked with an asterisk, to be used later. Then,v_O=V_O+ v_o is substituted as well. From this point we should realize that v_o is an amplification of v_i , giving an equation v_o= A*V_i where A is the amplification.
Removing the terms of V_O ( the bias point equation), and neglecting higher order terms of v_i, we will get v_o=- (k*R_L(V_I - V_T))*v_i.
v_o=- g_m*R_L*v_i where g_m=k*(V_I - V_T) so v_o=- A*V_i . A is a constant w.r.t. v_i
Lecture Notes:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/lecture-notes/
To make the MOSFET operate in the saturation region, the signal first needs to be boosted by applying a DC value, a DC voltage source, V_I , then after that apply a signal of interest, V_A which operates within the saturation region.
The output is an inversion of the input and there is a fair bit of distortion as the saturation region is not a straight line. There is amplification for sure but the signal is distorted so the amplifier is non linear.
How do we get a linear amplifier? This can be done with the small signal trick, where we focus on a small piece of the non-linear curve. So after boosting with a DC voltage, the input voltage needs to be shrunk to a small signal that gives a linear response.
Let's look at the small signal method
(1)graphically, (2) mathematically, and (3) from a circuit viewpoint - in the next sequence.
(1) Graphically, recall the small Signal Model Notation where v_I (total variable)= V_I (dc bias) + v_i (small signal) and v_O=V_O + v_o. From this method we will notice that a linear output can be obatined.
(2) Mathematically, first we need to substitute v_I=V_I+ v_i into
v_O=V_S -( k/2(v_I - V_T)^2)*R_L. The Bias Point Equation is V_O=V_S - (k/2(V_I - V_T)^2)*R_L and this is marked with an asterisk, to be used later. Then,v_O=V_O+ v_o is substituted as well. From this point we should realize that v_o is an amplification of v_i , giving an equation v_o= A*V_i where A is the amplification.
Removing the terms of V_O ( the bias point equation), and neglecting higher order terms of v_i, we will get v_o=- (k*R_L(V_I - V_T))*v_i.
v_o=- g_m*R_L*v_i where g_m=k*(V_I - V_T) so v_o=- A*V_i . A is a constant w.r.t. v_i
so the circuit behaves linearly for small signals.
Another way is to differentiate v_O=V_S -( k/2(v_I - V_T)^2)*R_L w.r.t. v_I taking v_I=V_I . This will be the slope at V_I. This value will need to be multiplied by v_i and it will be equal to v_o as v_o/v_i is equal to the slope. (see lecture 7 for a similar case)
Saturday, February 27, 2016
Revision of Circuits and Electronics - MOSFET Amplifier Large Signal Analysis (Lecture 9)
Video:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/video-lectures/lecture-9-part-1/
Lecture Notes:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/lecture-notes/
There needs to be a device that has a control port and output port which is a VCCS. It turns out that the MOSFET under certain conditions will do what is needed to be done.
The MOSFET has a gate , drain and a source terminals but it does not look like the VCCS which is a four terminal device. In order to make it look like the VCCS, the source terminal needs to be shared with the input and output port. To work, some voltage needs to be applied between the gate and source terminals and that is treated as the input port. Then there will be a current that goes from the drain to the source terminal.
The MOSFET has a high input gate resistance so a very small current is needed to turn it on. For the course, the input current is taken as zero. The on-state behaviour of the MOSFET is a bit more complex than the ideal switch or switch resistor model. When v_GS is more than V_T , the MOSFET is turned on.
What really happens as can be seen graphically (i_DS vs v_DS), is that the MOSFET behaves like a resistor in the beginning (small v_DS) but later saturates and behaves like a current source. Saturation occurs when v_DS is more than or equal to v_GS minus V_T. The triode region is where the MOSFET behaves like a resistor. The saturation region is where it behaves like a current source.
For different values of v_GS, the current through the MOSFET changes. When v_GS is lower, the current will also be lower.
In the saturation region, i_DS is some function of v_GS.
i_DS=k/2 ( v_GS - V_T)^2
For digital designs, the SR model is used. For analog models, the SCS model is used. This is the model where the MOSFET behaves like a dependent current source (saturation region).
In more advanced courses, a combination of SR and SCS models can be used.
To ensure the MOSFET operates as a VCCS , it must be operated in the saturation region only so it needs to adhere to the saturation discipline. This is the case where v_GS is more than or equal to V_T AND v_DS is more than or equal to (v_GS - V_T).
Let's analyze the circuit. First, replace the MOSFET with its SCS model.
i_DS=k/2 ( v_GS - V_T)^2 for the saturation region where v_GS is more than or equal to V_T AND v_DS is more than or equal to (v_GS - V_T).
There are two ways of analyzing the circuit- (1) the analytical method (2) the graphical method.
How does the output change with respect to the input (v_O versus v_I) ?
Node analysis is used. The equation for I_DS is substituted into the equation obtained from nodal analysis. A result v_O=V_S - (k/2(v_I - V_T)^2)*R_L is obtained for the saturation region. v_O=V_S when the MOSFET is off.
For the graphical method, the equations for v_DS (marked as A) and v_O (marked as B) are used.
Graphs of i__DS versus v_DS for the rearranged equations of A and B will be plotted.
Saturation begins at a point where v_O = v_I - V_T . This equation is substituted into the equation marked A giving an equation i_DS=(k*v_O^2)/2 to find where saturation begins.
Equation B is rearranged to get i_DS=(V_S - v_O)/R_L .
The plot of the rearranged equation of B known as the load line is then superimposed on the plot of A. Given a value of V_I, I_DS and V_O should lie on the load line.
Large signal analysis of amplifier has two steps -
(1) v_O versus v_I
(2) Find valid input operating range and valid output operating range (to guarantee saturation region operation.)
The graph of v_O versus v_I is plotted. First take note of V_T. When v_I is less than V_T, the MOSFET is in the cut-off region and v_O =V_S. When v_I is more than or equal to V_T AND v_O is more than or equal to (v_I - V_T), the MOSFET is in the saturation region and v_O=V_S - (k/2(v_I - V_T)^2)*R_L. When v_O is less than (v_I - V_T), the MOSFET is in the triode region. For example when v_I=3V and V_T=1V, then the v_O point where it gets into the triode
region = 3-l = 2V
The saturation region is the valid region for analog systems. The cutoff region and the triode region are for digital systems.
The valid operating ranges under the saturation discipline is the loadline that meets the boundary of the cut off region and the boundary of the triode region. The point at cutoff occurs when i_DS=0 (v_I=V_T ) and v_O=V_S. The point at the triode region is solved from the two equations of i_DS :-
i_DS=(V_S - v_O)/R_L and i_DS=(k*v_O^2)/2
Equating these two equations, it is possible to get a quadratic equation. The solution of this quadratic equation is v_O=(-1+((1+2*K*R_L*V_S)^0.5))/(k*R_L)
With that solution, it is possible to find v_I and i_DS. v_O=v_I - V_T at the boundary of the triode region so v_I=v_O + V_T .
Another way of obtaining the valid operating range is using the v_O versus v_I curve. The valid input operating range lies between v_I=V_T and the boundary point of the triode region where v_I=v_O + V_T. The valid output operating range lies between v_O=V_S and v_O=v_I - V_T.
To get the point at the triode region graphically, recall that v_O=v_I - v_T. If you draw the line v_O=v_I , you will find that v_O=v_I - V_T is a translation of v_O=v_I. From the translation, the point can be obtained graphically. The other point at the cutoff region boundary is at (V_T, V_S).
To get the point at the triode region mathematically, substitute v_O=v_I - V_T into
v_O=V_S - (k/2(v_I - V_T)^2)*R_L and solve for v_O. Once v_O is obtained, v_I= v_O + V_T.
Lecture Notes:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/lecture-notes/
There needs to be a device that has a control port and output port which is a VCCS. It turns out that the MOSFET under certain conditions will do what is needed to be done.
The MOSFET has a gate , drain and a source terminals but it does not look like the VCCS which is a four terminal device. In order to make it look like the VCCS, the source terminal needs to be shared with the input and output port. To work, some voltage needs to be applied between the gate and source terminals and that is treated as the input port. Then there will be a current that goes from the drain to the source terminal.
The MOSFET has a high input gate resistance so a very small current is needed to turn it on. For the course, the input current is taken as zero. The on-state behaviour of the MOSFET is a bit more complex than the ideal switch or switch resistor model. When v_GS is more than V_T , the MOSFET is turned on.
What really happens as can be seen graphically (i_DS vs v_DS), is that the MOSFET behaves like a resistor in the beginning (small v_DS) but later saturates and behaves like a current source. Saturation occurs when v_DS is more than or equal to v_GS minus V_T. The triode region is where the MOSFET behaves like a resistor. The saturation region is where it behaves like a current source.
For different values of v_GS, the current through the MOSFET changes. When v_GS is lower, the current will also be lower.
In the saturation region, i_DS is some function of v_GS.
i_DS=k/2 ( v_GS - V_T)^2
For digital designs, the SR model is used. For analog models, the SCS model is used. This is the model where the MOSFET behaves like a dependent current source (saturation region).
In more advanced courses, a combination of SR and SCS models can be used.
To ensure the MOSFET operates as a VCCS , it must be operated in the saturation region only so it needs to adhere to the saturation discipline. This is the case where v_GS is more than or equal to V_T AND v_DS is more than or equal to (v_GS - V_T).
Let's analyze the circuit. First, replace the MOSFET with its SCS model.
i_DS=k/2 ( v_GS - V_T)^2 for the saturation region where v_GS is more than or equal to V_T AND v_DS is more than or equal to (v_GS - V_T).
There are two ways of analyzing the circuit- (1) the analytical method (2) the graphical method.
How does the output change with respect to the input (v_O versus v_I) ?
Node analysis is used. The equation for I_DS is substituted into the equation obtained from nodal analysis. A result v_O=V_S - (k/2(v_I - V_T)^2)*R_L is obtained for the saturation region. v_O=V_S when the MOSFET is off.
For the graphical method, the equations for v_DS (marked as A) and v_O (marked as B) are used.
Graphs of i__DS versus v_DS for the rearranged equations of A and B will be plotted.
Saturation begins at a point where v_O = v_I - V_T . This equation is substituted into the equation marked A giving an equation i_DS=(k*v_O^2)/2 to find where saturation begins.
Equation B is rearranged to get i_DS=(V_S - v_O)/R_L .
The plot of the rearranged equation of B known as the load line is then superimposed on the plot of A. Given a value of V_I, I_DS and V_O should lie on the load line.
Large signal analysis of amplifier has two steps -
(1) v_O versus v_I
(2) Find valid input operating range and valid output operating range (to guarantee saturation region operation.)
The graph of v_O versus v_I is plotted. First take note of V_T. When v_I is less than V_T, the MOSFET is in the cut-off region and v_O =V_S. When v_I is more than or equal to V_T AND v_O is more than or equal to (v_I - V_T), the MOSFET is in the saturation region and v_O=V_S - (k/2(v_I - V_T)^2)*R_L. When v_O is less than (v_I - V_T), the MOSFET is in the triode region. For example when v_I=3V and V_T=1V, then the v_O point where it gets into the triode
region = 3-l = 2V
The saturation region is the valid region for analog systems. The cutoff region and the triode region are for digital systems.
The valid operating ranges under the saturation discipline is the loadline that meets the boundary of the cut off region and the boundary of the triode region. The point at cutoff occurs when i_DS=0 (v_I=V_T ) and v_O=V_S. The point at the triode region is solved from the two equations of i_DS :-
i_DS=(V_S - v_O)/R_L and i_DS=(k*v_O^2)/2
Equating these two equations, it is possible to get a quadratic equation. The solution of this quadratic equation is v_O=(-1+((1+2*K*R_L*V_S)^0.5))/(k*R_L)
With that solution, it is possible to find v_I and i_DS. v_O=v_I - V_T at the boundary of the triode region so v_I=v_O + V_T .
Another way of obtaining the valid operating range is using the v_O versus v_I curve. The valid input operating range lies between v_I=V_T and the boundary point of the triode region where v_I=v_O + V_T. The valid output operating range lies between v_O=V_S and v_O=v_I - V_T.
To get the point at the triode region graphically, recall that v_O=v_I - v_T. If you draw the line v_O=v_I , you will find that v_O=v_I - V_T is a translation of v_O=v_I. From the translation, the point can be obtained graphically. The other point at the cutoff region boundary is at (V_T, V_S).
To get the point at the triode region mathematically, substitute v_O=v_I - V_T into
v_O=V_S - (k/2(v_I - V_T)^2)*R_L and solve for v_O. Once v_O is obtained, v_I= v_O + V_T.
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