Wednesday, October 19, 2016

Circuits and Electronics - Energy and CMOS Design (Lecture 27)

Video and lecture notes:- edX    MITx: 6.002.3x Circuits and Electronics 3:  week 6

How do we get rid of the static power of our inverter?

So first  draw the equivalent circuit for the inverter when the MOSFET is in its on state.
That will be the case when the input is high. And the average power is going to be V_S squared divided by RL plus R on. RL is usually much bigger than R on, so the power will be
approximately VS squared divided by RL.
So this is my problem case.

When the input is low, then the MOSFETis in its off state. The average power in this case is zero.

However, in the former situation, I don't have any switch, and so therefore, I get this current flow from V_S to ground, and that's not a good situation.

So the question, then, is how do I somehow change this situation? So here is the trick.
What if, in place of RL,  I could get a switch in there. And somehow, when vI was high, the switch was open. If I could get my pull up switch to go open for the input being high, then I would have accomplished my goal. In that situation, I get no static power being burned when the input is high.
So this is good.

So in order to figure out what to use, I'm going to first show you a little bit more about the MOSFET that we have been using. The MOSFET that we have been using is called the N-channel MOSFET.
This is also called an NFET. So the NFET is complimentary to something else called the
PFET or the P-channel MOSFET.  Let me first very quickly review the properties of the N-channel MOSFET. And this MOSFET is on when V_GS is greater than or equal to V_T. The same MOSFET is off when V_GS less than V_TN.

Now let's take a look at something else-- a new device, a device that we haven't seen so far.
This device is called a P-channel MOSFET. In this case, the P-channel MOSFET doesn't have a channel where electrons carry current. And the P-channel creates a channel in the MOSFET where
the current is carried by what are called holes. Hole is an absence of an electron. And in some respects, it kind of behaves like a postive charge. The P-channel MOSFET is also called the PFET.
The PFET has complimentary properties to the N-channel MOSFET. And in the case of the P-channel MOSFET, it is on when V_GS is less than equal to a threshold voltage, V_T. The switch is off when V_GS is greater than V_T.

So now that we have this new complimentary gate, the P-channel MOSFET, let us consider
the following circuit. What I'm going to do, in this circuit I'm going to replace
our usual pull-up resistor with a PFET. And I had a N-channel MOSFET connected.

We can study  the behavior of the circuit by drawing out the equivalent circuit under the situation that v_I is high, and the second situation, v_I being low. We will find that this does not have static power.

But then, as we try to build chips with more and more gates in them at higher and higher frequencies, we realize that even those chips, their power kept increasing as well. And so we had to do something about the dynamic power too.

And it turns out that I'm going to do something about my voltage, and I'm going to do something about my capacitance.

Reducing voltage is not going to last all that long. One trade off, though, is as I reduce the voltage, as I go lower and lower in terms of my voltage, I cannot run my circuit as fast. That's a trade off.
In other words, in the same technology, a supply of 0.7 volts will result in a slower chip than a
supply of one volt.

 We can do something about the capacitance. And it turns out that, as I shrink my process--
recall that the reason I can put more and more transistors on a chip is because I use what I call process shrinks, I make my transistors smaller and smaller with each process generation.

And it not only shrinks the transistor, but recall the capacitor relates to the gate area of the transistor, and the transistor is shrinking, so is the capacitance. If we shrink my capacitors substantially, we can reduce my power significantly as well.

There's more tricks that people play. And one of the example tricks is when the circuit is not in
use, we just turn off the clock, and you go into standby mode.

Not only that, but when you are running the circuit, if some piece of the circuit is not in use-- so let's say for example, I am busy doing bit-level logic operations. If I'm doing bit-level logic operations, perhaps my floating point multiplier unit is not in use, and so I can turn off the clock to my floating point multiplier. So that concept where I turn off the clock to certain parts of the circuit is called clock gating. What I do is I pass my clock through a gate to some piece of the circuit. So I can turn off the clock with the clock enable signal.

There are other tricks that people follow today, and one of those is you change V_S depending on need. The problem is that the lowest voltage will result in the circuit not running fast enough.
So what I could do is, by default, have the circuit running at a low voltage and a low clock speed, and its performance is pretty mediocre. But when I really, really need the performance-- let's say, for example, the user is running a presentation and there's a video that has to be shown involving a lot of
computation. During those times, what I can do is up the voltage and up the frequency so the user can get a bit of a performance boost. But the power will be high as well, but it will be high only for a short period of time.

 notice that from 5 volts, chips in the 2007, 2008 time frame and beyond have gone down to about 1 volt, and as we go from 2012 to '13, '14 and '15, the voltage will go down further, to about 0.8,
0.7, and possibly even 0.6, 0.5 volts, in the middle part of the decade, now in 2014 or 2015.
But it is getting very, very difficult to lower the voltage beyond that. So the key point here with these real numbers is that, by reducing the capacitance, as we've gone from a 700 nanometer technology generation to a 45 nanometer technology generation for the Intel Nehalem, the 8 core
part, or the Tilera 64 core part, we've gone down to very low voltages.

Notice that transistors have gone up by almost a factor of 1,000, 2.5 million to over a billion transistors. Frequency has also gone up by a substantial factor, from 66 megahertz by 50 times, almost 100 times, to 3 gigahertz and beyond. But the power has stayed more or less the same, because all the tricks of the trade that I've talked previously have been applied. So the one point I wanted to make and not leave you with the impression that CMOS logic has only dynamic power.
I want to point out that in recent times, as transistors have gotten smaller and smaller, as they're heading to 45 nanometers, 32 nanometers, 22 nanometers and beyond, we do get to see something called leakage. Leakage causes a form of static power. And the leakage happens because, as the transistors get smaller and smaller, some amount of current can blast through the gate of the transistor, even when the transistor is off. Simply think of it as the gate having a very  high resistance, a non-zero high resistance. And when you have more than a billion transistors on a chip, even if the resistance is very, very high, you have a billion transistors sitting, leaking ever so slightly, you have some leakage power.

So if this is my transistor, and the transistor is on, I get a R_on. R_on is very low. Very low resistance. However, when the transistor is off, ideally I'd like infinite resistance. However, in reality, I end up with R off, which is high, but not open circuit. That causes a small leakage current. And when you have billions of transistors, and getting to two, three, four, eight billion transistors in a chip,
and if each of those transistors is sitting around leaking even slightly, you can have a substantial amount of leakage power, which has become the new static power.

The leakage related static power can be anywhere from 5% all the way up to 50% or 60% of the power. What is interesting about the leakage is that this relates to temperature. As the temperature increases, leakage increases.

So the interesting part is, my leakage goes up, my power goes up. And as my power goes up, my chip temperature goes up. As my chip temperature goes up, my leakage goes up. So this ends up being a little bit of a positive loop like system, and can hurt chips quite significantly if they're not designed very carefully to take into account the negative effects of leakage current

The last part is a review of  CMOS logic design where a NAND gate can be implemented by two PFET in parallel and two NFET in series.

Thursday, October 6, 2016

Circuits and Electronics - Energy and Power (Lecture 26)

Video Lectures: -

Lecture Notes: -

This sequence will pull together a lot of what you have learned throughout this course.
And look at it from the energy and power standpoint. Energy is extremely important.

So for example, if you have devices like your handheld, or your laptop, and other such stuff, energy relates to how long the battery will last in your cellphone. How long the battery will last in your laptop. The battery life relates to two things. One is, you've seen in cellphone usage when you look
at the specs of your cellphone, it talks about how long the phone the last in standby mode.
That means when you're not actively talking on your phone, if you just leave the phone on but you don't use it.

Another aspect of energy and power is when we build chips, oftentimes we don't care so much about battery life, but simply if the chip is consuming too much power,

Finally, a really important point is that we really need to reduce our energy consumption. In this sequence we will learn about how we can calculate the amount of energy and power consumed by the kind of circuits we've been building. And then look at ways in which we can reduce the power

 We will study energy and power dissipation, and use the MOSFET gate as an example.
So here on the right-hand side, you see a MOSFET gate. It's an inverter. So we have the pull-up resistor here.

What I've also done here is I'm showing you a capacitor, C, that I'm connecting between the output and the ground for this inverter. This capacitor might combine a set of capacitors connected to
the output. So for example, this capacitor might include the capacitance of the gate of a MOSFET that it might be driving. This capacitance also includes the capacitance of the wire or the wires connected to the output of the inverter. So think of this capacitor, C, as the total capacitance
connected to the drain of the MOSFET or the output of the inverter.

So what I'm going to focus on here is I'm going to determine both the standby power, or static power, and the active use power. So standby power relates to the power consumed by the inverter when it is not in active use. In our context here, it means the following. It means that if I keep the input at 0 or 1. I'm not going to change the input.  Clearly, if the input is a 0, then the MOSFET is going to be in its off state, and it's not going to burn any power, any standby power. This is also called static power.

So the standby power, or static power, has to do with when I don't change any of the inputs to my devices, and it's just sitting there idle. And the static, or standby, power relates to the power
consumed in that state.

Then there is the active use power. For active use power, let us say I supply some time varying input.
Let's say I supply a sequence of 1's and 0's. Let's say I apply a square wave, which is a sequence of
1's and 0's. And when that happens, when the MOSFET is switching on and off, there is some extra power consumed by the inverter-- and we'll see why that is the case-- when it's switching back and forth. This is called active use power. We will look at both cases.

So the first example that I want to do is a very, very simple example that you saw in the very
beginning of this course. So in this example, I'm going to have a voltage source. Imagine it's a DC source, an even simple example, connected to a simple resistor. So let's try to figure out two things.
One, let's figure out, just as a quick review, what is the power dissipated in the resistor. Second, what I want to do is once we compute the power dissipated in the resistor, I want to find out what is the
energy dissipated in the resistor in some given period of time.

Remember, the power is the rate of consumption of energy. So we can also figure out what the energy dissipated is in some interval of time T. This is very simple.

So I'd like you to switch to a little exercise where you can try out this conceptual problem yourself and try to solve for both the power and the energy dissipated in the resistor time T.

So the power burned by the resistor- consumed in the resistor is simply the voltage across the resistor times the current into the positive terminal of the voltage, as I've labeled across the resistor. So power is simply P equals voltage times the current. So the energy would simply be the power, in this case P,
times T. And since power is voltage times the current, the energy will be VIT.

The voltage is in volts, the resistor is in ohms, and the power will be in watts.

So the next example I'd like to do is look at the static power dissipated in our gate based on the example that we have just seen. So for our gate, let's try to figure out what the static power is on the standby power. The static power is simply the power consumed by the gate when it is not switching.
In other words, when I don't have some kind of a one zero or other pattern that is making the gates switch. So the choice is either zero or a one at the input to figure out the static power. So for our gate, I can write down two situations. When the input is high, here is my situation. I still have Vs over here. My load resistor Rl- this should be l over here. And when the gate is turned on, the MOSFET is on, I have the MOSFET in its on state. I'm using the SR model for the MOSFET.

So let me write that down as the SR model being used. So I have an Ron for my MOSFET.
Here is when I take my output Vo. I have my input Vi with respect to ground. OK? And this is in its high state. It's one. So when it's a one, the MOSFET is on and the situation I've drawn here is the one that applies to the gate. So in this situation, based on the previous little example that we did, the power P simply going to be Vs squared divided by the resistance through which the voltage is
connected to ground. So it is simply Vs squared and I have a pair of resistors, Rl and Ron.
So I get Rl plus Ron here. So that is my power consumed by the gate when the input is in its high state.

The second situation is when the input is low, so Vi is in its low state. Under those conditions, the MOSFET is going to operate like an open switch. It still has the resistor Ron but the MOSFET will be in its open state. And from here, I connected to Rl as usual and this goes to Vs and this is my output, V not. So in this situation, where is the power being consumed by the inverter here?
The static power here is simply zero. And the power is zero because there is no current flowing
from Vs to ground because of the open circuit that is the
open MOSFET.

So, in general, if I have a bunch of inverters and a bunch of gates in my circuit, if the input to the gate is high, then I'm going to get some static power being burned by the inverter or other gate.
On the other hand, if the input is low, the MOSFET is going to be high, MOSFET is going to be in its open state and it is not going to burn any power. So in general if I have 1,000 gates in my circuit --
imagine there are 1,000 inverters-- then if I pick voltages, inputs randomly then to be zero or a one, half the MOSFETs are expected to have one at their input and the other half will have zero at
their input. So, by and large, half the MOSFETs will be burning power and half will not. And so, therefore, I take the amount of power consumed by one MOSFET and multiply that by half the inverters to find the expected power dissipation of the circuit.

In the next example, I'm going to be beginning to introduce dynamic power or active power.

 In the previous video, we looked at the static power for the MOSFET gate, that is, when the inputs were a 0 or a 1. Now what I'm going to do is I'm going to do a slightly different example. In this example, I'm going to lead up towards how to compute the dynamic power of the inverter. That is when the input to the inverter is switching between 1's and 0's.

Now, doing that for the inverter directly is a little more complicated . And so we are  going to start with a much simpler circuit and build up intuition in terms of how to compute the power that gets dissipated because I'm switching a capacitor, charging and discharging a capacitor.

So the circuit that I'm going to use is going to be the following. I take a voltage source, a VS. I'm going to connect that to a switch, S1. And then I'm going to connect that to a resistor, R1.
And that, in turn, will connect to a capacitor with capacitance C and complete the circuit
for the voltage source. Then I take the connection between the resistor R1 and the capacitor and connect it to a second switch, S2, which, in turn, will go to another resistor and then connect that
back, like so, a resistance R2. All right, what we are  going to do next is  we are going to switch
switches S1 and S2 in the following manner. We are going to first switch S1 on and S2 off.
So I'll switch S1 on first and S2 off. So by doing so, I'm going to charge up the capacitor.
Then what I'll do is I'll switch off S1 and turn S2 on so that the capacitor now, because S2 is turned on and S1 is off, this capacitor will discharge through R2.

There will be a repetitive cycle. The time period is T.  And our goal will be to find out a couple of things.  One goal will be to find the energy dissipated in each cycle. And the second thing will be to find the average power.

So there are two periods, T1 and T2.  So let me go ahead and start with T1. And I'm going to consider the first case, S1 closed and S2 open.
The initial condition on the capacitor  starts off at 0. And as a function of time, the capacitor's
going to charge up. As the capacitor keeps charging up, it looks like a long-term open circuit.
VS will completely charge up the capacitor. And after a long period of time, its final value is going
to settle down at VS And it's going to have some rising transient that look like this.
So the form of that rising transient will be 1 minus e raised to minus T over the time constant.
What are the time constant for this circuit? Well, it's R1 C.

Similarly, I can plot the current i.

Instantaneous power be supplied by source, by the voltage source, is going to be V_S times i.
The voltage times the current is my instantaneous power.  The energy will simply be the time integral of the instantaneous power over that interval of time. And I will integrate that from 0 to T1 dt.

 i is V_S over R1 e raised to minus t over R1 C. So we end up getting integral 0 to T1 and V_S squared divided by R1 e raised to minus t over R1 C dt. We will eventually get C V_S squared.

So what we're really saying here is C V_S squared is the energy supplied by the source, total energy supplied by the source in T1.

So the total energy supplied by the source, C V_S squared, one part of it is stored on the capacitor, which is 1/2 C V_S squared stored on capacitor. Well, since the capacitor is being charged through a
resistor, the other half of the energy must have dissipated in R1. Let E1 be the energy dissipated in R1.

What is interesting here,  is notice that when time T1 is large enough, that these two energies, the energy supplied by the source, the energy dissipated in the resistor, or for that matter, the energy
stored in the capacitor are independent of  resistance R1.

 E2 is the energy dissipated in the resistor R2 during time interval T2. Both E1 and E2 are independent of R2 and both are equal. E1 was half C V_S squared, and so is E2.

Total energy dissipated cycle, where the cycle is T1 plus T2, the total energy, E, will be the sum of the two energies, E1 plus E2, where E1 is the energy lost in T1 and E2 is the energy is lost in T2.
So it's E1 plus E2. And the total is CV_S squared.

What about the average power? The average power is simply going to be the total energy
burned in the whole cycle, T1 plus T2, energy divided by the total time, T. So T is simply T1 plus T2.
Now, recall that T is the reciprocal of the frequency of switching. So, average power is CVS squared f where f is the frequency.

All right, thus far, we examined two examples. In the first example, we just took a voltage source across a resistor and computed the static power. And we showed that directly related to the static power in an invert when it had a one or a zero applied at the input. We did a second example.
In the second example, we took a capacitor and we used a pair of switches to charge and discharge the capacitor. But notice that when switch one was turned on, switch two was turned off. Switch two was turned on, switch one was turned off. That is not quite the situation in the inverter.

So back to our inverter. Our goal was really to find out P for the inverter. And recall again, this capacitor C is the capacitor of the gate capacitance of the gates being driven by this inverter and also any parasitic capacitance of the wires and things like that. So to compute the power in this particular situation, I would like to pick some input - a zero one sequence-   a square wave.

So we need to  figure out the average power.  So let's start by drawing the equivalent circuit for my
little inverter here which consists of viltage source V_S, R_L,  capacitor C and R_ON.

So this equivalent circuit to compute the average power.  So it actually turns out that the derivation of the power consumed by the circuit, first by computing the energy and then dividing by the cycle time t is a little bit more complicated and grubby than the circuit we did earlier.

So we can show that the average power for the circuit is given by this expression. So here we have two terms, Vs squared divided by 2 R_ON plus R_ON plus CVd squared vf, CVs squared f. R_L squared divided by R_ON. plus R_ON. all squared. R_L might be 100 times larger than R_ON. So I'm going to neglect R_ON in comparison to R_L.

I get a very simple expression for P. The term on the right hand side is my dynamic power or
active power. So static power is simply the power being burned in R_L because of a connection from Vs through RL to ground. And then the second term, the dynamic power is because I'm switching the capacitor and putting charge in the capacitor and discharging it. Dynamic power will increase in proportion to f, the frequency. The static power is independent of the frequency and the half term comes-- the half shows up because the static power is consumed only for half the cycle.
The MOSFET is on only for half the time. Notice interestingly, that both the static and dynamic
powers relate to the square of the voltage. What that is saying is that the voltage that I apply has a
profound impact on the power being burned.

The amount of capacitance matters and the frequency matters for the dynamic power. But Vs has a profound impact on the power. Dynamic power can be lowered by reducing Vs and the frequency but
if we change the clock frequency,  then  computational speed goes down as well.

Chips are typically about 10 millimeters on a side, so one square centimeter. The chips are square, flat little pieces of silicon. And then if I take a one centimeter squared area at roughly the surface of the sun, it can be seen that they have the same output power.

Sunday, September 11, 2016

Circuits and Electronics - Op Amps Positive Feedback (Lecture 25)

 Video Lectures: -

Lecture Notes: -

Positive and negative feedback of op amps give the same output but positive feedback cannot possible work that way. In reality a small disturbance in the positive feedback amplifier output  will cause the output to increases until it reaches saturation. Static analysis of positive feedback does indeed yield v-out equals minus R2 over R1 times v-in but better tools will be needed to analyze positive feedback.

Static analysis of positive feedback circuit is done with a dependent source model.  Nodal analysis is used. This does not really work so a dynamic model is used instead. This dynamic model consists of a  resistor, capacitor and a dependent source.

A positive and negative feedback is connected to the dynamic model. The dynamic model  is analyzed by first finding the values of v_plus and v_minus in terms of the fraction of the voltage output. Then the node method is applied to the capacitor. What we would be left with is a differential equation which has a solution  v_0 equals K e to the minus t divided by capital T.

We will see how the system behaves with  respect to t, which in turn behaves on gamma minus and
gamma plus. So we first plot v_0, which is equal to K, a small disturbance. So we have to  look at various situations. So let's say we start with t being positive and  t will be positive when gamma minus is greater than gamma plus. This will result in a slope that is going down. If gamma minus is greater than gamma plus, negative feedback is stronger than positive feedback. In other words, net, I am feeding more of the output to the negative terminal than to the positive terminal. So if the  negative feedback is stronger than my positive feedback, then what's going to happen is  output, k, is
going to very quickly go down to 0. So that is my stable situation. Not surprisingly, you recall, for op amps with negative feedback, if  there is  a perturbation to the output, very quickly that would go to 0 because of the negative feedback.

So in this situation, if gamma plus is greater than gamma minus, in other words, if
positive feedback is stronger- then t is negative. What we will notice is that there is no minus sign
in the exponential, and so therefore, my response is going to spiral out of control leading to an 
unstable situation.

And then what happens when- the natural thing to consider next is when gamma plus more
or less equal to gamma minus. In this case, t is very large and  v_0 is more or less equal to K for a
long period of time. This is called neutral equilibrium.

We could build a number of interesting circuits with the op amp without negative feedback.
Again, recall when the op amp doesn't have negative feedback, it is going to move with any slight perturbation. It is going to try to hit the positive rail, Vs, or it's going to hit the negative rail, Vs.
So in this particular instance, in the op amp portal I want to show you Vs plus and minus Vs explicitly so you know that Vs and V minus Vs are the positive and negative supply. So the op amp is going to hit those values, depending on what the input is. So the first circuit is a comparator.
What is a comparator? A comparator is a circuit where, when an input is applied, the output is going to shoot to either a plus, a Vs, or a V minus, depending on whether the input is positive or negative.
In this case, what I'll do is I'll connect V minus to ground. So V minus is set at zero volts. I want to apply an input to V plus. So my input, Vi, is applied to V plus. So now, what's going to happen is that when Vi is greater than zero volts, the output is going to shoot positive.  And if Vi is less than zero, the output is going to shoot to a negative, minus Vs. So this is a comparator. What it does is that the output is a high if the input is positive, and the output is a low if the input is negative. So we can build a transfer function of the comparator. We can also do a time behavior out  of this.

A comparator  has a lot of uses. It can be used  to tell  whether the input is positive or negative. And it can also used to  to take the analog signal and turn that into a one bit digital value, a zero, one kind of sequence at the output, for a positive and negative going analog signal as an input. Now, one of the issues with a comparator like this is that it has the unfortunate property that small perturbations, or small noise imposed at the input, can cause weird, unexpected behavior 

Let's say my input looks like there's some noise imposed on the input. If we focus on  a certain part  right where there isn't a clean crossing,  the part where the signal is crossing the zero line, the output is going to go bouncing back and forth causing some spikes.

So we are  going to use positive feedback to build what we call hysteresis not run the op amp
in the open loop mode like this. By building hysteresis into the circuit, we will make the circuit remember what happened in the past, so that it doesn't behave so flippantly as did the open loop op amp.

So here's my op amp,with  v_I as in the past. And what we are going to do is apply positive feedback. In this case, a resistance R2, a resistance R1, and  connect the voltage divider between R2 and R1 to the positive terminal. And this is my output v_0 taken with respect to ground. For this example, let us assume, just for fun, that R1 is equal to R2, so that, at the center here, this is v_0 divided by 2 where R1 equals R2.  Let's assume, to be specific, V_S is equal to 15 volts.  So let's say, because the output is at 15 volts, v plus is therefore at 7.5 volts. So as soon as vi reaches plus 7.6 volts, the output is going to swing hugely negative, and hit the negative rail, minus 15 volts.

The moment the output hits minus 15 volts, then, as the sixth step, v plus goes to minus 7.5 volts.
So v plus goes to minus 7.5 volts. So what happens then? If v plus goes to minus 7.5 volts,  there is  a big negative voltage between v plus and v minus. So at that point, even if the voltage vi begins to meander around 7.5  let's say, because of noise, from 7.6 it goes to 7.7. No problem. v plus minus v minus is still negative. What if at that point, v minus goes to 7.4? Amazingly enough, no change in the output. Why is that? If vi goes to 7.4 volts because of noise instantaneously, notice that, because v plus, through positive feedback, has now switched to minus 7.5 volts, this is a huge negative offset.

So let me draw you a little chart so you get a better sense of what is going on here.
So I could draw what's called a state diagram. These state diagrams tend to capture the memory property of these circuits. And notice that my op amp circuit has two states.
One state is where the output v0 is equal to plus 15 volts, and the second state is where the output
v0 is minus 15 volts. Two states. In the first state, notice that v plus is at 7.5 volts, and in the second state, v plus is at minus 7.5 volts. I have two states there. So let's use a state diagram to understand
what we've just built. So you recall I said life started out with me being the first state, v0 equals plus 15 volts, so I start off in this state. And I said I started off with vi being 0. Then what happened was vi went past 7.5 volts. So if vi became greater than 7.5 volts, what happened? When vi became greater than 7.5 volts, then my output switched to the second state. Eventually we will notice that in this circuit, we have a memory in the system. That is, this state here, the v0 equals minus 15, remembers that vi had gone above 7.5 volts. And once it went above 7.5 volts, this state says, OK,
it is  not going to change until vi then goes below negative 7.5 volts. It remembers that.

We are going to plot vi versus vo in this diagram. The output is a memory property here.
The circuit remembers the past. And that is called hysteresis. This is, if you recall, many of you have played with magnets and so on, and you can magnetize some of these materials, and that's where the term is used commonly, And that property which remembers what happened during the past is called hysteresis.

Now, why is this useful? This is useful, as you will be able to get a clean wave form at the output because of the memory property.

OK, so now let's take a look at another fun circuit called the oscillator. Again, circuits like this can be used to build what we call a clock. So before we look at what clocks are useful for, let's
try to build an oscillator. An oscillator is a circuit that oscillates back and forth by itself between high voltage and a zero voltage. We'll call it high voltage and a low voltage. And there are many fun uses for a circuit like that. OK, let's build a circuit and then talk about some applications of a oscillator.
In this fun circuit, we would apply both negative and positive feedback.

,Let  us  start with what you've seen before and apply some positive feedback using a usual R and R voltage divider like so. Since R and R are equal, then the voltage at my positive input is simply going to V naught divided by 2. At the negative terminal, we are  going to build an RC circuit.
Notice that  current cannot go into the minus terminal because it's infinite resistance.And so that current, 15 volts divided by R, has nowhere to go, but it's going to start charging up the capacitor.
So as the capacitor starts charging up, it eventually charges to 7.5 volts,  And when it charges to 7.5 volts and exceeds it ever so slightly, boom, I'm going to have a negative voltage on the V plus minus V minus terminal pair, and the output is going to switch negative.

And I'm going to have a negative 7.5 volts now at the plus terminal, the capacitor is at plus 7.5 and the output is at minus 15. So in this case, what's going to happen is that, because the output is at minus 15 volts, the current is now going to flow in the right-hand direction so the capacitor is going to start discharging now because this has switched from plus 15, which is charging the
capacitor, to minus 15 that will begin discharging the capacitor. So as the capacitor begins to discharge and the voltage  will start going more and more negative, ultimately, the voltage gets to minus 7.5 volts, in which case this switches to plus 15. It switches to plus 15 and begins to charge up the capacitor again, and so on and so forth.

Let's now get some insight into how to compute the frequency of oscillation.
First, to find the frequency of oscillation, we are going look to find the time period of oscillation,
 and a rise time.So what I'm going to do is start by trying to figure out the rise time of the capacitor voltage, that is this time.

Once the system goes into a steady state, recall that, for the rise, the capacitor voltage is going to go up from minus Vs by 2 all the way up to plus Vs by 2. So let's go ahead and try to figure out what that time is. So this is vC, the capacitor voltage. So to figure out vC, I could write down in general, for a rising capacitor voltage, the intuitive method of figuring out the rise time is the following.
So vC will be some initial voltage on capacitor, initial voltage on capacitor plus the change in voltage times 1 minus e raised to minus t over RC. The change that we're talking about is the voltage that the capacitor would have reached had it gone all the way to its high value.

Starting at Vs minus 2 and, if left to itself, the capacitor would've gone all the way to Vs. That is what we have to use for this formula. So in this formula, the initial value is simply minus Vs over two.
That's the initial value in the capacitor. So we can solve this equation for tr and that gives the rise time.

A similar method is used to find the fall time.

A clock is a square wave that's applied to digital systems. And the clock can be useful for senders and
receivers to communicate effectively.
OK, as an example, suppose I have a sender and a receiver. And the sender wants to send some values. So let's say the sender really wants to send the sequence of values, 1, 1, 0, as in the waveform shown here, OK? Also notice that the waveform is a little funny, in the sense that I have a 1 and 1.
I have a high part of the waveform out here with the 1 and 1 with the low part of the waveform showing 0, but then a part of the waveform where the signal is a bit funky. So for example, it could be that the output of the gate that is producing the waveform, because of parasitic capacitance and impedances, may have some ringing associated with it.

OK, so the receiver is sitting there trying to figure out when is the signal valid.  You can say the receiver can look at the signal when the clock is high, for example. That's the example I'm using here. In other cases, with what is called edge-triggered logic, you can tell the receiver, look at the signal during a given clock edge, a rising edge or a falling edge. But in our example, I'm simply going to say that the sender needs to make sure that a valid signal is available to the receiver whenever the clock is high.

So notice here the receiver is looking at the output from the sender whenever the clock is high.
Notice that the first time the clock is high, it picks up a 1. Then it picks up another 1. Then it picks up a 0 out here, OK? So it picks up a 0 at the point where the clock is high for the third time because the receiver sees a 1, 1, 0. And the receiver is pretty happy with that. So what we have done here using the clock is another kind of discretization. It is discretizing time, rather than dealing with
continuous time, by using a clock. 

Notice that discretization of time is one among another major sequence of discretizations that we do in systems to make it all work, OK? Recall, in physics, we had the discrete mass or lumped mass
discipline where we lumped matter and got the point mass simplification. Then, for the digital discipline, we discretized value, and we got the digital abstraction. And now we've talked about discretizing time, So this is a pretty cool sequence of things that we do to make systems easy to design and build.

Thursday, August 25, 2016

Circuits and Electronics - The Operational Amplifier Circuits (Lecture 24)

Video Lectures: -

Lecture Notes: -

We first look at the subtractor circuit. There are five steps in the first method of obtaining v_O.
Another way is the superposition method which is the easier way. The two input voltages are shorted one at a a time, v_1 is set to zero, then v_2 is set to zero. After that the output voltages are added.

Next, we look at how to build an integrator. As voltage output is proportional to the  integral of the current, we need to somehow convert voltage v_I to a current. First, we try using a resistor to do so. This can happen when v_O is very small compared to v_R..
However we will find that that this is not possible as the capacitor tends to charge up v_O to a certain value.

The better way is an op amp integrator. With KVL, v_O=v_C.

To build a differentiator  as current  is proportional to the differential  of the input voltage , we need to somehow convert  current to a voltage v_O.  The circuit is somewhat similar to the integrator except the resistor and capacitor are swapped.

Filters can be built with op amps as well. The problem with passive filters is that it is difficult to get v_O  equal to H of j omega v_I.

The moment a load resistance is connected to the filter circuit, the j omega of the filter has changed.

When a a source with an internal resistance R_I is connected to the filter circuit, the filter characteristic will change as well. Worse is that the filter resistance loads the source, so the source may not be able to supply current.

The other issue is that it is difficult to build an inductor in an integrated circuit. As many filter circuits require inductors , we need to look at some other approach of doing such things. The approach is to use op amps and the first approach is known as the brute force approach. In this approach a buffer is used. A buffer can be connected to the input and the output but it is a bit inefficient.

We will see how op amps work with impedances. and sketch a graph for values of low and high omega. In this case, a bandpass filter is obtained.

We can build non linear circuits with op amps. With an inverting amplifier, it is possible to build an exponentiator with the Expodweeb device.

With that in mind, it is possible to build a logarithmic amplifier.

Summing amplifiers can be used to build digital to analog converters.

Thursday, August 11, 2016

Circuits and Electronics - The Operational Amplifier Abstraction (Lecture 23)

Video Lectures:-

Lecture Notes:-

The Operational Amplifier  an input port represented with a plus and a minus. That's where the  input signal is applied. Then there is an output port.

There are two terminals for the input. So I have a pair of terminals, plus minus, and the input is applied  across those two terminals.  This has what is called a differential input.

It also has a power port, and here we go. The way the power port works is with both a positive and negative supply.

A more abstract representation for the op amp is one without the power supplies.

 We will look at a    very simple equivalent circuit for an ideal op amp. For the input, you are going to have a pair of terminals.

And let's say the input is v. So v is the voltage difference between the two terminals. And then, the output of the op amp comes from a dependent ideal, a dependent source -  an ideal voltage-controlled voltage source. So let's say this is what it looks like from between ground and out here, that is v_O.
And for this dependent voltage source, its voltage is going to be Av, where A is a very large number.
Where A tends to infinity. And in practice, A is typically 10 to the 6, or thereabouts. And so notice that v is v plus minus v minus.

Av, the output v_0, can also be written as A times v plus minus v minus.

Both input terminals display an open circuit. So therefore, my current going in is going to be identically equal to 0 at all times. And this is ideal op amp so i plus equals 0 where i plus is
the current into the plus terminal. And similarly, i minus is equal to 0. So both i plus and i minus, the currents into the plus and minus terminals of the op amp are identically equal to 0. That says that there's an open circuit at the inputs of the operational amplifier.

I have a dependent voltage source, it's a voltage source at the output. So therefore, it has 0 output resistance.. What about the input resistance? Resistance looking into the plus terminal is infinity.
Similarly, resistance looking into the minus terminal is infinity. And the reason is that i plus is identically equal to 0 at all times. And so is i minus. So , infinite input resistance.

For the ideal op amp, there is no saturation - what this is saying is that the output voltage v_0 can
take on any value.

So let's very quickly summarize what we've seen so far. So for this ideal op amp, the current into the positive terminal is 0, infinite resistance. Current into the negative terminal is also 0, infinite
impedance there as well. The voltage between the plus minus terminal pair is v. And my output is modeled as a voltage-controlled voltage source. It's a dependent voltage source. And the voltage is going to be Av. It's going to be amplifying the input voltage difference between the terminal pair by A. And because it's a ideal dependent voltage source, the output resistance is 0. And then A, the gain, is virtually infinity for this ideal op amp.  Op amps are the basic building block of the analog industry. Most analog designs are done with such abstractions. We may have more detailed piece of information that we use in the op amp model. Maybe make it less ideal.

So a  range of voltages V_I is applied to the input of the MOSFET. And we are going to plot V_I versus V_0 for the MOSFET  show  the concept of saturation. So we're going to have our op amp with +12 and -12V power supplies shown as well. It's not going to be the perfectly ideal op amp, where there is no saturation.  And then, for  V_0, there will be  a resistor, R_L.

The input voltage V_I is going to be swept across a range of values So that as I sweep the values of VI across a range of values, I want to go ahead and observe what V_0 looks like. Now, recall, from the diagram up here, recall that V_0 is equal to A times V. A might be on the order of 10 to the sixth. Given that V_0 is A times V, I'm going to have a huge, huge gain.

For a small change in V_I, there is  going to be a massive change in V_0. So we will see  a V_0 versus V_I with a huge slope.  If A is on the order of 10 to the sixth, then for a 10-microvolt input--
OK, so in this case, I have 10 here minus 10 here. So for a 20-microvolt input, if A is 10 to the sixth, what's going to happen here is that when  some point is reached --  at +12-volt and -12V, there will be saturation.

The region, where the output is truly A times V, is called the active region. And when you use the MOSFET, generally, when you build linear devices, that is where you want the MOSFET to operate.

So far, so good, but one of the issues here is that this A , even though it's about 10 to the sixth or thereabouts, it's really, really unreliable. Among other things, A could be temperature dependent.

So even though A is really large, the op amp can behave weirdly as its temperature changes.

Now, how do we get to use the op amp?

Where by using a little trick, a little trick called feedback, we are going to make the op amp behave exactly like we want it to.

So we have the abstract op amp here on the left and  the equivalent circuit of the op amp on the
right-hand side.

 A circuit will be built and connected to the abstract op amp. And then an equivalent circuit diagram with the same circuit, will be built  so  that A and other parameters can be analyzed.The circuit is a
non-inverting amplifier. It's going to be an amplifier that's going to gives some gain, a small amount of gain. And it's going to pass the input without inversion.

We will eventually end up with an equation involving v_0 and v_I and we have to make an approximation  where A is very large.  We will get  v_0 is approximately equal to v_I
times r1 plus r2 divided by r2.

It can be seen that the non-inverting op amp provides a stable output even when heat is applied. This is due to negative feedback. To explore how this happens, we have to perturb the output voltage from 10 V of 12 V. Recall that the output of the op amp is A times v plus minus v minus.  6V is fed back to the inverting terminal, making the output decrease. Then part of the output is fed back again, this time causing the output to increase.

The key is that the stable point is when v plus equals v minus. It's not exactly equal. It's more or less equal to each other. Because notice that the moment one of them becomes greater than the other, the output tends to shoot in one direction.

From the virtual short method, it's only negative feedback that causes V-plus to be more
or less equal to V-minus. We also know a couple of other constraints, that I-plus and  I-minus is 0. The  method  solves  op amp circuits really, really quickly. And the beauty of this technique is that we don't have to deal with the A and all of that stuff anymore.

On examining the buffer circuit with the virtual short method , we can see that the voltage output follows the voltage input. Another method is putting  R_1=0 and R_2= infinity.

So why is this circuit useful?

Notice that one might think that we could just take v_I and just connect it to whatever system we want to connect it to. But the problem is that this v_I may be a very sensitive sensor. It's some kind of a sensor. And it cannot provide much current. So this system that it is connected to may damage the
sensor or cause its behavior to change.

So buffers are useful in this situation, where you want to buffer the output from the input. Buffers serve as really nice isolation devices. So let's look at the properties of this buffer.

The voltage gain is simply 1.
The impedance looking in is infinity.
The output impedance is 0.
The current gain is infinity.
The power gain is also infinity.

These are pretty good statistics. That's why a buffer is very useful, to isolate sources that are quite sensitive from other uses in the rest of the system.

Next, we look at an inverting amplifier circuit. Start by grounding the V plus terminal.  Notice that in all of these negative feedback circuits, some portion of the output always gets fed back to the
negative terminal. So here,  output is fed back to the input  with  R1.  And then, the input  resistance,  R2  and input voltage are connected.

We are going to use both the op amp equivalent circuit and the virtual short method to analyze the circuit  and just show you how simple the virtual short method makes it.

The principle of superposition is employed in the op amp equivalent circuit model. So V-minus will be the sum of the components of voltage at V-minus due to V_I and V_0.

Next, we look at the input resistance of an inverting amplifier circuit. To do this we need to  apply a test input v_I, and measure the current i_I going in. So then the Rin is going to be v_I divided by i_I.

To get the input resistance, we have to find i_I in terms of the resistances, v_I and v_O. Then we substitute the value of v_O. Conductance is used for the analysis. Eventually we will get a value of input resistance equal to R_2. The virtual short method is much faster for this case.

Sunday, July 3, 2016

Circuits and Electronics - Time Domain Versus Frequency Domain Analysis (Lecture 22)

Video and lecture notes:- edX    MITx: 6.002.3x Circuits and Electronics 3:  week 3

Identifying the time domain behavior of the circuit is easy from the impedance analysis.
Because if you recall, for our RLC circuit, Vc over Vi from the previous video was given by omega naught squared divided by s squared plus 2 alpha s plus omega naught squared. The s was equal to j omega. Now, you can get the time domain behavior completely from this equation here. OK, if you recall, at a given point in our analysis, we had substituted e to the st for a response, and when we
differentiated e to the st with respect to time, we got s e raised to st. And the e raised to st things canceled out. So each time you saw a d by dt, we ended up with an s in our equation.

So what we can do is  a reverse mapping. So wherever we see an s, we can go and stick in a d by dt
there and derive the differential equation in a backward step. Wherever you see an s squared, stick in a second derivative.

However, just for kicks, let's say we care about a step input. So for example, let's try a step input.
So for a step input, the input signal will simply be some dc value starting at time t equal to 0.
There you go. So I've very quickly written my differential equation for a step input for the same circuit completely by using frequency domain analysis.

 As before, even if I did the time domain analysis, my Q is the same, omega naught by 2 alpha, and
for the series RLC circuit, 2 alpha is R divided by L. So I ended up with omega naught divided by R over L, which is Q.  We will look at using  Q at both time domain and frequency domain behavior.

For  the frequency domain, we would apply a sinusoid  given by Vi cosine omega t. For the time domain, just for fun, we are going to use a unit step.   And as we have seen in the past, we can do the analysis in three cases.

So one case is for overdamped behavior. So for this overdamped behavior, alpha is greater than omega naught.  And in terms of Q, Q-- which is equal to omega naught by 2 alpha-- is less than 1/2.

Then for alpha less than omega naught, or Q--which is still omega naught by 2 alpha-- is greater than 1/2. this is high Q. This is underdamped.

And then, finally, a look at alpha equals omega naught. And in this case, Q equals 1/2. This is critically damped.

With the over-damped case,  alpha is greater than omega naught. This is the over-damped case. In one case,  a sinusoid is applied at the input and  the frequency response is measured. We are going to measure the magnitude of Vc/Vi, the magnitude of the transfer function for the frequency response. For the time domain part, we are  going to apply a unit step and   observe for what v_C looks like.

For the frequency domain behavior, it looks like a low-pass filter. It's low-Q, no peakiness.
And at the time domain,  there is a pretty sluggish circuit, which just goes up lazily and saturates at unity.

For the  underdamped case,  alpha is less than omega-naught. And so therefore, Q will be greater than half. Again, this is the case where I'm going to get a high Q circuit. So in this case, what's going to happen is that at omega-naught, because I have a high Q filter, I am going to get a peaky response.
The bandwidth is defined as the interval between the points in the curve where the response falls to 1 by square root 2 of the peak value. And 1 by square root 2 is 0.707. And sometimes it's also called the 0.707 frequency at which you reach the 1 by square root 2 value. Either way, it's a narrow band, and it's a very high Q filter. What happens in the time domain? Underdamped circuits gave rise to a lot of ringing. They were not sluggish. So for this capacitor's circuit, it would eventually settle down at 1.
So for instance, if I have a Q of 50, then the circuit is going to sit around ringing for about 50 rings.
And of course, notice that if I make R close to 0, if R goes close to 0, then this just becomes LC.
And recall, for an LC circuit, it will ring forever. Provide a unit step, they will simply ring forever
and ever and ever. Because Q for that circuit would be infinity when R goes to 0. So the key here is that in the time domain, Q relates to how ringy the circuit is. Q relates to ringiness. And in the frequency domain, Q relates to peakiness.

Finally, let me look at the critically damped case where alpha equals omega naught or, equivalently, Q equals half. Same circuits, input sinusoid for the frequency domain analysis and unit step for the time domain analysis. So in the case of my frequency domain analysis, let me first draw out clearly, at the very low and very high frequencies, the circuit behaves similarly. And it will look something like . . . 'bloop'.  Next, let's look at the time domain behavior of the same circuit and for the step input. I just get a little, little blip. It may be seen that  correlated to a flipped version of the time domain
step response but don't get confused by that.

Thursday, June 30, 2016

Circuits and Electronics - Filters (Lecture 21)

Video Lectures:-

Lecture Notes:-

We often build special circuits known as filters  to eliminate that specific frequency of 50 to 60 Hz from the signal as AC in most countries are at 50 or 60 Hz. Otherwise we end up with a very low hum.

First, we need to plot the graphs of impedance against omega  for capacitors, resistors and inductors.
For very low frequencies, the impedance of the capacitor is very, very high. The capacitor looks like an open circuit but for very high frequencies, the capacitor looks like a short circuit. So for the capacitor, we will be able to see  the curve that shows its impedance.

For a  resistor R,  its behavior is frequency independent. So its impedance is simply R. And so it is
going to be a constant.

For the inductor, notice that for  very low values of omega, the impedance  is very low, and for high values of omega, the impedance is very high. Not surprisingly, the inductor looks like an open circuit to high frequencies and for DC and very low frequencies, the inductor looks very much like a short circuit.

So let's start with a CR circuit. If we plot the magnitude of H of omega of the transfer function for this filter, what does it look like?
So let's start with the high frequencies just for fun. For very high frequencies, note that the capacitor is a short circuit. And the resistor, of course, has a resistance R. So the capacitor is a short circuit and so Vi will appear directly at Vr. So for very high frequencies, my filter will give me Vi at Vr. So Vr divided by Vi will simply be unity.

What about for very low frequencies? At very low frequencies, the capacitor behaves like an open circuit. And if that behaves like an open circuit, then most of the voltage drop will be across the capacitor and very little will drop across the resistor and so I'm going to get a very low value. So low value for low frequencies and high values for high frequencies. So what we will get is a high pass filter.

 These same principles apply for an RC circuit.  So for an RC circuit, we will get a low pass filter.

 For an RL circuit, at low frequencies,  the inductor behaves like a short circuit so  H of omega  will have a low value. At high frequencies, the inductor behaves  like an open circuit, so H of omega  will have a high value. The RL circuit will be a high pass filter.

For an RLC circuit with the output voltage  measured across the resistor,  a  bandpass filter is produced. At resonance, omega equals omega0  which is  1 by square root of LC  and H of omega will be equal to 1.

For an RLC circuit with the output voltage  measured across the capacitor and inductor,  a  bandstop filter is produced. At resonance, the output voltage is zero.

For an RLC circuit with the output voltage  measured across the capacitor and inductor in parallel,  a  bandpass filter is produced. At resonance, the output voltage is zero. A major application of bandpass filters is in AM radio.  The capacitor is made variable so that the bandpass filter can tune to various frequencies.

How does the radio work?
On the x axis of the graph  is the frequency of the signal. On the y-axis, is the  signal strength.
So the way radio system work is that different radio stations would be transmitting at different frequencies. So, for example, in the Boston area, there are a bunch of radio stations that transmit the following frequency. So for example, one of the radio stations is 1030 in the Amplitude Modulation band, And then,there may be  other signals being transmitted by other radio stations. So for example, there may be a  station transmitting at 1020, another at 1010 KHz  and it goes on and on.
So when stations transmit, they try to maximize its signal strength, say  around the 1030 frequency, ,it tries to maximize it there. And then it tries to make sure that the signal strengthdoesn't encroach too much into neighboring bands.So notice that each of these stations  gets a roughly 10 kilohertz band.
So let's say, if I want to listen to WBZ News Radio, then I have to tune my capacitor here such that
the band-pass filter have its passing band focused where I care the most.

So when this is passed through, this band-pass filter will allow the 1030 range to mostly get through, and it will attenuate everything else that's further away but it is not  perfect and so it will let through a little bit of the neighboring bands.  That's why with AM radio you always get some interference from the sides of the two neighboring bands.

Fundamentally, that is a small value. Mostly the  1030 will come through. So this was the filter, the band-pass filter

Notice here that selectivity is important.
What is selectivity? Selectivity has to do with trying to capture the signal in a given range.
In the next video, we will see that the selectivity relates to something that you've seen before.

It will be shown how  a RLC circuit, gives voltage values that are much higher than voltage values that are input. We have to look at  Vc divide by Vi.. If the graph of  Vc divide by Vi against omega  is plotted, we will get a low pass filter.

We can do the maths with  Vc over Vi using the voltage divider relation. We can write the impedance of the capacitor and divide it by the sum of all of the other impedance.

And for the magnitude, we can  simply get the square of the real part plus the square of the
imaginary part square rooted.

You've taken it on faith from me that between these two points the function looks like the graph but that is not true.

Next we need to find out mathematically what happens at resonance. After some mathematical analysis, it can be seen that  V_c  is equal to Q times V_i. If Q is very large,  V_c  is more than V_i.

Next, we look at  RLC circuit with V_r  divided by V_i. We will get  a bandpass filter.

So selectivity, we saw this in the context of radios. Selectivity has to do with how selective my filter is. Recall this is a band pass filter And selectivity says, how sharp is this band? How selective am I?
So one way of figuring out selectivity is to look at this ratio omega 0 by delta 0. Where delta 0 is called the bandwidth, it's measured at the point where the various parts of the curve reaches 1
by square root 2 of its highest value.

So higher omega 0 by delta omega, higher the selectivity. So the reason is that as delta omega becomes narrower, my filter becomes more selective.

For the  next part, we need to find out what is delta omega. Absolute magnitude of  V_r  divided by V_i   is one by square root 2. Eventually we will get a result of delta omega equal to R/L.

As  2 alpha is equal to R divided by L so  omega 0 by delta omega is equal to Q. The lower the R, the sharper the peak, the more selective the filter. So high q implies high selectivity.  From  Q, you can tell all kinds of things about that circuit.

Q can also be defined as 2 pi times the energy stored in the circuit divided by energy lost per cycle in the circuit.