Sunday, March 13, 2016

Revision of Circuits and Electronics - Digital Circuit Speed (Lecture 14)

Video Lectures:- http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/video-lectures/lecture-13/

Lecture Notes:-  http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-002-circuits-and-electronics-spring-2007/video-lectures/lecture-13/


An intuitive  approach can be taken to plot the responses to various inputs. There are two kinds of waveforms for the capacitor or inductor circuits- exponential decay  e^(-t/RC) and another one with an expression  (1-e^(-t/RC)) 

 Plotting the graph of v_c versus t , for  the case V_I > V_0, we can see that the capacitor will charge  up, so the waveform with the expression (1-e^(-t/RC)) is picked.  The waveform with the expression (1-e^(-t/RC))  starts off at 0  and ends at 1, which  looks something like (1-0)(1-e^(-t/RC))  so the  capacitor circuit should have  (V_I -V_0)(1-e^(-t/RC)) as part of the expression for v_c.  It can also be seen  from the graph that at time t=0,   v_c=V_0 , and (V_I -V_0)(1-e^(-t/RC))=0 so the  final equation should be v_c=V_0 +  (V_I -V_0)(1-e^(-t/RC)) with V_0 being  the initial value.

 For the case where V_I 0,  we can see that the capacitor will discharge, so the waveform with the expression e^(-t/RC) is picked. The waveform with the expression e^(-t/RC)  starts off at 1  and ends at 0, which  looks something like (1-0)(e^(-t/RC))  so the  capacitor circuit should have  (V_0 -V_I)(e^(-t/RC)) as part of the expression for v_c.  It can also be seen  from the graph that at time t=0,   v_c=V_0 , and (V_0-V_I)(e^(-t/RC))=(V_I -V_0) so the  final equation should be 
v_c=V_I +  (V_0 -V_I)(e^(-t/RC)).

 Applying the result to two inverters, we will need to draw out the circuit, which are two pairs of resistor and MOSFET. The capacitor is between  the gate and the source  of the MOSFET.  There are two delays at B(the input of the second inverter)  - the rising delay, the delay when the signal is rising and the falling delay. For cleanliness, the focus will be on the capacitor at B. 

 Suppose that the voltage at A ( input to the first inverter) is going   from 5V to 0V -from logical 1 to logical 0, then the output of it, which is B will switch from logical 0 to logical l. So we will need to figure out the rising delay at this point.

 Due to the capacitor at B, the output at B will be a waveform with the expression (1-e^(-t/RC)). The rising delay or t_r is the  time taken to reach the valid value for a high signal V_OH.

We  need to figure out what is the equivalent circuit that can compute the rise time.  It is generally around the output at B.  From there, we have to assume that the output at B starts at 0V. So  we need to find out how long it takes to go from 0V to V_OH. 

When A goes from 5 volts to 0 volts, the MOSFET for the first inverter  turns off and so the capacitor at node B starts to charge up from 0 to V_S. Therefore the equation will be  v_B=  V_S(1-e^(-t/RC)) . So we need to find the time t  it takes for v_B to reach V_OH.

The rising delay t_r= R_L*C_GS*ln((V_S-V_OH)/V_S). This value is quite close to the time constant RC so for a quick answer to the value of the rising delay, the time constant can be used.

 If t_r=0.16 ns,  the frequency will be  1/t_r=6GHz but there are  generally 10 to 20  delays, so for 10 delays,  the frequency will be 6/10 GHz = 600 MHz.

 Next, we need to figure out the falling delay. Falling delay is simply the time for which v_B to  fall from V_S  to V_OL. So it starts out with   the first   inverter  off, and so v_B has charged up to VS.  Now, the moment this inverter switches to its on state, when the input at A goes from 0 to 1 ihen this MOSFET, which comprises gate x, will turn on.  As soon as it turns on, then not only do I have a VS
connection through R_L to node B, but also the  R_ON resistance.  v_B(0)= V_S=5V

Thevenin's theorem can be used.   V_TH=V_S (R_ON/(R_ON+R_L))  and 
R_TH=(R_L*R_ON)/(R_L+R_ON).  The capacitor will discharge from a voltage of V_S to V_TH.
The exponential decay is governed by the time constant RC.

 The time constant RC=R_TH*C_GS. the equation will be  
v_B=  V_TH+(V_S -V_TH)( (e^(-t/(R_TH*C_GS))) . So taking V_B=V_OL  , the falling delay
t_f= R_TH*C_GS*ln((V_OL-V_TH)/(V_S-V_TH)).

 Once again, the value of the time constant is  close to that of t_f.   The effect of R_ON  has made the time constant smaller resulting in a smaller falling delay (waveform falls faster).

There may be times when slower may be  better.  A real life example was when a  group of students in a university built a chip  which had input and output pins. What they were hoping to see from the output was a nice little step from a low voltage to a high voltage. What they saw was a slow rise. So they thought they could make a faster wave by reducing the resistance  but what they got was a waveform with many glitches.

 The solution was to slow down the edges  of the waveform.  There  was a parasitic capacitance between the pins which had caused the glitches.







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