Wednesday, April 20, 2016

Revision of Circuits and Electronics - State and Memory (Lecture 16)

Video Lectures: -

Lecture Notes:-  (Lecure 14 on OCW but lecture 16 on edX)

The key is that a capacitor can store a a state for an extended period of time.

The equation for RC charging circuit is v_c=v_c(0)+  (V_I -v_c(0))(1-e^(-t/RC)) .  We ignored what happened all the way from minus infinity. v_c(0) was able to summarise the entire behaviour of the input from 0 backwards.

State is the summary of past inputs relevant to predicting the future.       q and v are state variables.

v_c was a function of v_c(0) and a function of V_I(t).

Zero state  is when v_c(0)=0.  Zero input  is when V_I(t)=0.

Zero state response (ZSR) occurs at  v_c=V_I (1-e^(-t/RC)). The capacitor charges up.

Zero input response(ZIR) occurs at  v_c=v_c(0)(e^(-t/RC)). The capacitor discharges.

The sum of the ZSR and ZIR gives the total response of the RC circuit   
v_c=V_I+  (v_c(0)-V_I)(e^(-t/RC)). This is a form of superposition.

Why memory? The calculator remembers the partial result.  It is needed to remember such results so that things can be done in sequence. Secondly, there is a need to remember transient inputs - signals that come and go away. Finally it is needed to store data.

With  this in mind, starting with a simple  example, a one bit memory element  can be built.   It will have d_OUT, d_IN and a STORE signal  which tells the memory cell to replace existing value with new value from d_IN.

A camera has a shutter button which helps to store the image. Think of this as a little pulse which opens to allow the image to be appear on the storage medium of the film and when it closes whatever that was recorded will stay in the camera.

Using this analogy, a simple memory cell can be built.  Let's say the waveforms for d_OUT, d_IN and STORE  start at a low value.  When d_IN goes high for a period of time ,  to store that value, a small STORE pulse can do the job. The STORE pulse is like a shutter release button. d_OUT will reflect what is at the input. The  last value that the memory cells saw  before the pulse went down to 0 is eventually stored in the  memory cell. The output does not go to 1 instantaneously, rather that it meanders up and rises slowly.

 In the first attempt to build a memory cell,  a capacitor is needed to store a value that is going to be read out, d_OUT. d_IN and a switch is connected to the capacitor. The control input of the s witch is connected to the STORE signal. When the STORE signal has a high value, the switch is closed.  If this is a perfectly ideal switch, and this is a true short circuit, and if d_IN comes from an ideal voltage source, then of course I'm going to see my capacitor charging instantaneously. However in pratice that is not the case - the switch has a resistor R_ON. So the capacitor has to charge through R_ON.

Let's say d_IN goes to a 1 and here is my store pulse that stays on for some period of time.
Let's say my dOUT is 0 to begin. As soon as the store pulse goes high, the switch goes into its On state. nd as soon as the switch goes into its On state, now the capacitor C begin surcharge through the resistor R_ON with the time constant, T given by R_ON*C. 

As the capacitor begins to charge, the voltage at dOUT starts to rise. So this is the voltage of v_c, which turns out to be the same as d_OUT. So that starts to rise, and when the store pulse goes
away, that value will be held out there.

We need to find out the width of the store pulse.  v_c=V_S (1-e^(-t/RC)) as this is a zero state response. The store pulse has to be wide enough for the v_c to charge to its valid high value V_OH.
Therefore V_OH=V_S (1-e^(-t_min/RC)) .  The pulse width needs to be much larger than t_min to give enough leeway for the capacitor to reach its final value.

Now with the store =0,  we need to find out how long is the charge going to sit on the capacitor. Suppose that the output is connected to some other circuit that has a load resistance R_L. In this case the capacitor will be discharging from a value V_S to a valid value V_OH. So we will need to find t_valid. 

 v_OH=V_S (e^(-t_valid/(R_L*C))) as this is a zero input response.  Therefore t_valid=-R_L*C* ln(V_OH/V_S). This method does not really work as the capacitor  discharges very quickly.

 The second attempt is to add a  pair of inverters (a buffer) to  the output.  The buffer has a large input resistance R_IN. The time constant is calculated to be about 1 millisecond which would give a better result for t_valid but still not good enough.

For the third attempt, the value is fed back  to refresh the node. There is a switch that is connected to STORE bar in this loop.  When STORE is a 0, the  same value at the output is recycled  to the capacitor and the capacitor  is meant to be refreshed. This does not work  because the external value can influence the storage node.

For the fourth attempt,  the feedback loop is now placed after the first inverter and is connected to another inverter and a switch. The switch  is connected to STORE bar.  This works as there is no path from the output to the input as it is completely decoupled using the inverter. This is a static random access memory (SRAM) where the value of the memory cell stays valid for a long period of time.

 An abstract 4 bit  memory cell has an input,  an output, a STORE signal and  an address line.  The address tells me which of the  four bits of memory I  am going to read or write. So the address is given by two bits 00 ,  01 , 10 and 11.    00 will read to memory cell 1, 01 to memory cell 2 and so forth. If my address says two and if store is false, then my output should read the second memory cell.  Similarly, if the address is two and store is on, then I should be writing into my memory cell two.

So to build the memory system, four memory cells are needed. The one bit output is connected to the four memory cells with switches A, B, C and D.  The values of A, B, C and D are produced with a decoder.  The address will be the input to the decoders while the outputs are connected to the A, B , C and D switches.

The INPUT is going to be connected to all d_IN. Then there will be AND gates which will be connected to the STORE signal and one of the  the outputs of the decoder. 

So let's take a look at how this works. So that say the address is 1, 0. If the address is 1, 0, then C is true.  And when the store pulse comes on, both inputs are a one. And I get a store pulse on this memory cell. And then whatever's on the input line gets written on to that memory cell. And then following that, if I'll reread the memory cell, I make the store pulse go away.  And if C is true, then the switch turns on. And the value can be read out on OUT.

From the truth table,  at any given point in time, only one of A, B, C, or D is a 1.  Memory cells
containing billions of memory elements are built using similar logic.

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