Wednesday, October 19, 2016

Circuits and Electronics - Energy and CMOS Design (Lecture 27)

Video and lecture notes:- edX    MITx: 6.002.3x Circuits and Electronics 3:  week 6

How do we get rid of the static power of our inverter?

So first  draw the equivalent circuit for the inverter when the MOSFET is in its on state.
That will be the case when the input is high. And the average power is going to be V_S squared divided by RL plus R on. RL is usually much bigger than R on, so the power will be
approximately VS squared divided by RL.
So this is my problem case.

When the input is low, then the MOSFETis in its off state. The average power in this case is zero.

However, in the former situation, I don't have any switch, and so therefore, I get this current flow from V_S to ground, and that's not a good situation.

So the question, then, is how do I somehow change this situation? So here is the trick.
What if, in place of RL,  I could get a switch in there. And somehow, when vI was high, the switch was open. If I could get my pull up switch to go open for the input being high, then I would have accomplished my goal. In that situation, I get no static power being burned when the input is high.
So this is good.

So in order to figure out what to use, I'm going to first show you a little bit more about the MOSFET that we have been using. The MOSFET that we have been using is called the N-channel MOSFET.
This is also called an NFET. So the NFET is complimentary to something else called the
PFET or the P-channel MOSFET.  Let me first very quickly review the properties of the N-channel MOSFET. And this MOSFET is on when V_GS is greater than or equal to V_T. The same MOSFET is off when V_GS less than V_TN.

Now let's take a look at something else-- a new device, a device that we haven't seen so far.
This device is called a P-channel MOSFET. In this case, the P-channel MOSFET doesn't have a channel where electrons carry current. And the P-channel creates a channel in the MOSFET where
the current is carried by what are called holes. Hole is an absence of an electron. And in some respects, it kind of behaves like a postive charge. The P-channel MOSFET is also called the PFET.
The PFET has complimentary properties to the N-channel MOSFET. And in the case of the P-channel MOSFET, it is on when V_GS is less than equal to a threshold voltage, V_T. The switch is off when V_GS is greater than V_T.

So now that we have this new complimentary gate, the P-channel MOSFET, let us consider
the following circuit. What I'm going to do, in this circuit I'm going to replace
our usual pull-up resistor with a PFET. And I had a N-channel MOSFET connected.

We can study  the behavior of the circuit by drawing out the equivalent circuit under the situation that v_I is high, and the second situation, v_I being low. We will find that this does not have static power.

But then, as we try to build chips with more and more gates in them at higher and higher frequencies, we realize that even those chips, their power kept increasing as well. And so we had to do something about the dynamic power too.

And it turns out that I'm going to do something about my voltage, and I'm going to do something about my capacitance.

Reducing voltage is not going to last all that long. One trade off, though, is as I reduce the voltage, as I go lower and lower in terms of my voltage, I cannot run my circuit as fast. That's a trade off.
In other words, in the same technology, a supply of 0.7 volts will result in a slower chip than a
supply of one volt.

 We can do something about the capacitance. And it turns out that, as I shrink my process--
recall that the reason I can put more and more transistors on a chip is because I use what I call process shrinks, I make my transistors smaller and smaller with each process generation.

And it not only shrinks the transistor, but recall the capacitor relates to the gate area of the transistor, and the transistor is shrinking, so is the capacitance. If we shrink my capacitors substantially, we can reduce my power significantly as well.

There's more tricks that people play. And one of the example tricks is when the circuit is not in
use, we just turn off the clock, and you go into standby mode.

Not only that, but when you are running the circuit, if some piece of the circuit is not in use-- so let's say for example, I am busy doing bit-level logic operations. If I'm doing bit-level logic operations, perhaps my floating point multiplier unit is not in use, and so I can turn off the clock to my floating point multiplier. So that concept where I turn off the clock to certain parts of the circuit is called clock gating. What I do is I pass my clock through a gate to some piece of the circuit. So I can turn off the clock with the clock enable signal.

There are other tricks that people follow today, and one of those is you change V_S depending on need. The problem is that the lowest voltage will result in the circuit not running fast enough.
So what I could do is, by default, have the circuit running at a low voltage and a low clock speed, and its performance is pretty mediocre. But when I really, really need the performance-- let's say, for example, the user is running a presentation and there's a video that has to be shown involving a lot of
computation. During those times, what I can do is up the voltage and up the frequency so the user can get a bit of a performance boost. But the power will be high as well, but it will be high only for a short period of time.

 notice that from 5 volts, chips in the 2007, 2008 time frame and beyond have gone down to about 1 volt, and as we go from 2012 to '13, '14 and '15, the voltage will go down further, to about 0.8,
0.7, and possibly even 0.6, 0.5 volts, in the middle part of the decade, now in 2014 or 2015.
But it is getting very, very difficult to lower the voltage beyond that. So the key point here with these real numbers is that, by reducing the capacitance, as we've gone from a 700 nanometer technology generation to a 45 nanometer technology generation for the Intel Nehalem, the 8 core
part, or the Tilera 64 core part, we've gone down to very low voltages.

Notice that transistors have gone up by almost a factor of 1,000, 2.5 million to over a billion transistors. Frequency has also gone up by a substantial factor, from 66 megahertz by 50 times, almost 100 times, to 3 gigahertz and beyond. But the power has stayed more or less the same, because all the tricks of the trade that I've talked previously have been applied. So the one point I wanted to make and not leave you with the impression that CMOS logic has only dynamic power.
I want to point out that in recent times, as transistors have gotten smaller and smaller, as they're heading to 45 nanometers, 32 nanometers, 22 nanometers and beyond, we do get to see something called leakage. Leakage causes a form of static power. And the leakage happens because, as the transistors get smaller and smaller, some amount of current can blast through the gate of the transistor, even when the transistor is off. Simply think of it as the gate having a very  high resistance, a non-zero high resistance. And when you have more than a billion transistors on a chip, even if the resistance is very, very high, you have a billion transistors sitting, leaking ever so slightly, you have some leakage power.

So if this is my transistor, and the transistor is on, I get a R_on. R_on is very low. Very low resistance. However, when the transistor is off, ideally I'd like infinite resistance. However, in reality, I end up with R off, which is high, but not open circuit. That causes a small leakage current. And when you have billions of transistors, and getting to two, three, four, eight billion transistors in a chip,
and if each of those transistors is sitting around leaking even slightly, you can have a substantial amount of leakage power, which has become the new static power.

The leakage related static power can be anywhere from 5% all the way up to 50% or 60% of the power. What is interesting about the leakage is that this relates to temperature. As the temperature increases, leakage increases.

So the interesting part is, my leakage goes up, my power goes up. And as my power goes up, my chip temperature goes up. As my chip temperature goes up, my leakage goes up. So this ends up being a little bit of a positive loop like system, and can hurt chips quite significantly if they're not designed very carefully to take into account the negative effects of leakage current

The last part is a review of  CMOS logic design where a NAND gate can be implemented by two PFET in parallel and two NFET in series.

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